Tso-Bing Juang
According to our database1,
Tso-Bing Juang
authored at least 26 papers
between 2002 and 2023.
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Bibliography
2023
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS).
Proceedings of the 20th International SoC Design Conference, 2023
2019
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems.
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems.
Proceedings of the International SoC Design Conference, 2018
2017
Proceedings of the International SoC Design Conference, 2017
2016
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the International SoC Design Conference, 2016
2014
Fast binary to BCD converters for decimal communications using new recoding circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2012
J. Circuits Syst. Comput., 2012
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders.
Proceedings of the International SoC Design Conference, 2012
A lower error antilogarithmic converter using novel four-region piecewise-linear approximation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Multifunction RNS modulo (2<sup>n</sup>±1) multipliers based on modified booth encoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
2010
Improved Area-Efficient Weighted Modulo 2<sup>n</sup> + 1 Adder Design With Simple Correction Schemes.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Corrections to "VLSI Design of Diminished-One Modulo 2<sup>n</sup> + 1 Adder Using Circular Carry Selection" [Sep 08 897-901].
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
2008
Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.
IEICE Trans. Inf. Syst., 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations.
IEEE Signal Process. Lett., 2004
2002
Partition methodology for the final adder in a tree-structure parallel multiplier generator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002