Mingjing Chen

According to our database1, Mingjing Chen authored at least 21 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Sleep apnea screening based on Photoplethysmography data from wearable bracelets using an information-based similarity approach.
Comput. Methods Programs Biomed., 2021

2019
Empirical Mode Decomposition as a Novel Approach to Study Heart Rate Variability in Congestive Heart Failure Assessment.
Entropy, 2019

2014
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2012
Tackling nanoscale IC failures through noise-aware testing and silicon debugging.
PhD thesis, 2012

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2012

On Diagnosis of Timing Failures in Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Diagnosing scan chain timing faults through statistical feature analysis of scan images.
Proceedings of the Design, Automation and Test in Europe, 2011

Diagnosing scan clock delay faults through statistical timing pruning.
Proceedings of the 48th Design Automation Conference, 2011

2010
Squashing code size in microcoded IPs while delivering high decompression speed.
Des. Autom. Embed. Syst., 2010

VDDmin test optimization for overscreening minimization through adaptive scan chain masking.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Scan power reduction in linear test data compression scheme.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Scan BIST with biased scan test signals.
Sci. China Ser. F Inf. Sci., 2008

Test cost minimization through adaptive test development.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.
IEEE Trans. Computers, 2007

Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.
Proceedings of the 25th International Conference on Computer Design, 2007

Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Decision Tree Based Mismatch Diagnosis in Analog Circuits.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006


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