Dong Xiang
Orcid: 0000-0003-4788-511X
According to our database1,
Dong Xiang
authored at least 145 papers
between 1992 and 2024.
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Bibliography
2024
ACM Trans. Design Autom. Electr. Syst., January, 2024
Disentangling Imperfect: A Wavelet-Infused Multilevel Heterogeneous Network for Human Activity Recognition in Flawed Wearable Sensor Data.
CoRR, 2024
2023
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., March, 2023
A Pose-Normalization Method for Casting Voxel Models Using Second-Order Central Moment Matrix.
IEEE Access, 2023
Heterogeneous Die-to-Die Interfaces: Enabling More Flexible Chiplet Interconnection Systems.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Accelerating Model Solving for Integrated Optimization of Timetabling and Vehicle Scheduling based on Graph Convolutional Network.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
J. Glob. Inf. Manag., 2022
Proceedings of the New Trends in Computer Technologies and Applications, 2022
Knowledge graph-based approach to trace the full life cycle information of decommissioned electromechanical products.
Proceedings of the 18th IEEE International Conference on Automation Science and Engineering, 2022
2021
Determinants of the Use of Fintech Finance Among Chinese Small and Medium-Sized Enterprises.
IEEE Trans. Engineering Management, 2021
Proceedings of the Computing and Combinatorics - 27th International Conference, 2021
2020
Deadlock-free adaptive 3D network-on-chips routing algorithm with repetitive turn concept.
IET Commun., 2020
Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
2019
IEEE Trans. Dependable Secur. Comput., 2019
An Innovative Virtual Simulation Teaching Platform on Digital Mapping with Unmanned Aerial Vehicle for Remote Sensing Education.
Remote. Sens., 2019
CCF Trans. High Perform. Comput., 2019
Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation, 2019
Proceedings of the Data Science, 2019
Construction of Ultimate Video Experience and Application Innovation System Based on 5G and 8K.
Proceedings of the Data Processing Techniques and Applications for Cyber-Physical Systems, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
Deadlock-Free Adaptive Routing Based on the Repetitive Turn Model for 3D Network-on-Chip.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018
2017
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing.
ACM Trans. Design Autom. Electr. Syst., 2016
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.
IEEE Trans. Computers, 2016
An Ultrasensitive Long-Period Fiber Grating-Based Refractive Index Sensor with Long Wavelengths.
Sensors, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
2015
J. Supercomput., 2015
Comparative study of coal, natural gas, and coke-oven gas based methanol to olefins processes in China.
Comput. Chem. Eng., 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Pingmesh: A Large-Scale System for Data Center Network Latency Measurement and Analysis.
Proceedings of the 2015 ACM Conference on Special Interest Group on Data Communication, 2015
A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs.
ACM J. Emerg. Technol. Comput. Syst., 2014
IEICE Electron. Express, 2014
Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Database Systems for Advanced Applications, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 12th IEEE International Conference on Trust, 2013
Proceedings of the IEEE 32nd Symposium on Reliable Distributed Systems, 2013
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 19th Asia-Pacific Conference on Communications, 2013
2012
IEEE Trans. Parallel Distributed Syst., 2012
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing.
ACM Trans. Design Autom. Electr. Syst., 2012
Multiple Spanning Tree Construction for Deadlock-Free Adaptive Routing in Irregular Networks.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Deadlock-Free Adaptive Routing in Meshes with Fault-Tolerance Ability Based on Channel Overlapping.
IEEE Trans. Dependable Secur. Comput., 2011
Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture.
J. Low Power Electron., 2010
IET Comput. Digit. Tech., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
An Effective Congestion-Aware Selection Function for Adaptive Routing in Interconnection Networks.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model.
IEEE Trans. Computers, 2009
Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
A power-effective scan architecture using scan flip-flops clustering and post-generation filling.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Conflict driven scan chain configuration for high transition fault coverage and low test power.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
J. Syst. Archit., 2008
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008
Proceedings of the 9th International Conference for Young Computer Scientists, 2008
Deadlock-Free Fully Adaptive Routing in Tori Based on a New Virtual Network Partitioning Scheme.
Proceedings of the 2008 International Conference on Parallel Processing, 2008
Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme.
Proceedings of the 28th IEEE International Conference on Distributed Computing Systems (ICDCS 2008), 2008
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008
2007
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.
IEEE Trans. Computers, 2007
IEEE Trans. Computers, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Fast and effective fault simulation for path delay faults based on selected testable paths.
Proceedings of the 2007 IEEE International Test Conference, 2007
Deadlock-Free Adaptive Routing in Meshes Based on Cost-Effective Deadlock Avoidance Schemes.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost.
Proceedings of the 16th Asian Test Symposium, 2007
2006
J. Parallel Distributed Comput., 2006
J. Mobile Multimedia, 2006
Future Gener. Comput. Syst., 2006
Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), 2006
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture.
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Parallel Comput., 2005
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
IEEE Trans. Computers, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Reliable broadcasting in wormhole-routed hypercube-connected networks using local safety information.
IEEE Trans. Reliab., 2003
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.
IEEE Trans. Computers, 2003
J. Inf. Sci. Eng., 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A cost-effective scan architecture for scan testing with non-scan test power and test application cost.
Proceedings of the 40th Design Automation Conference, 2003
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the Advanced Parallel Programming Technologies, 5th International Workshop, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
IEEE Trans. Parallel Distributed Syst., 2001
Local-Safety-Information-Based Broadcasting in Hypercube Multicomputers with Node and Link Faults.
J. Interconnect. Networks, 2001
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 2001 IEEE Symposium on Security and Privacy, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Non-scan design for testability for synchronous sequential circuits based on conflict analysis.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1998
Proceedings of the Advances in Neural Information Processing Systems 11, [NIPS Conference, Denver, Colorado, USA, November 30, 1998
1996
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Autom. Control., 1995
1994
Structural properties of optimal production controllers in failure-prone manufacturing systems.
IEEE Trans. Autom. Control., 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
1993
IEEE Trans. Autom. Control., 1993
1992
Proceedings of the Fifth International Conference on VLSI Design, 1992