Minje Jun

According to our database1, Minje Jun authored at least 11 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems.
IEEE Trans. Computers, 2014

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis.
IEEE Trans. Computers, 2014

2012
Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network.
IEEE Trans. Computers, 2012

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2010
Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning.
Comput. J., 2010

Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Topology Synthesis of Cascaded Crossbar Switches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Latency-Aware Bus Arbitration for Real-Time Embedded Systems.
IEICE Trans. Inf. Syst., 2007

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007


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