Jean-Luc Gaudiot

According to our database1, Jean-Luc Gaudiot
  • authored at least 232 papers between 1982 and 2017.
  • has a "Dijkstra number"2 of four.

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to the programmability and reliability of dataflow architectures.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2017
Embedded Systems Architecture for SLAM Applications.
CoRR, 2017

Enabling Embedded Inference Engine with ARM Compute Library: A Case Study.
CoRR, 2017

CAAD: Computer Architecture for Autonomous Driving.
CoRR, 2017

Implementing a Cloud Platform for Autonomous Driving.
CoRR, 2017

Learn-Memorize-Recall-Reduce A Robotic Cloud Computing Paradigm.
CoRR, 2017

Computer Architectures for Autonomous Driving.
IEEE Computer, 2017

Computer, Drive My Car!
IEEE Computer, 2017

2017: The New Computer Society.
IEEE Computer, 2017

PETRAS: Performance, Energy and Thermal Aware Resource Allocation and Scheduling for Heterogeneous Systems.
Proceedings of the 8th International Workshop on Programming Models and Applications for Multicores and Manycores, 2017

A Runtime Workload Distribution with Resource Allocation for CPU-GPU Heterogeneous Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Reevaluating the overhead of data preparation for asymmetric multicore system on graphics processing.
TIIS, 2016

Extending Amdahl's Law for Heterogeneous Multicore Processor with Consideration of the Overhead of Data Preparation.
Embedded Systems Letters, 2016

Engineering the New Boundaries of AI.
IEEE Computer, 2016

Codelet Scheduling by Genetic Algorithm.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

The Importance of Efficient Fine-Grain Synchronization for Many-Core Systems.
Proceedings of the Languages and Compilers for Parallel Computing, 2016

PETS: Performance, energy and thermal aware scheduler for job mapping with resource allocation in heterogeneous systems.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016

2015
Network Variation and Fault Tolerant Performance Acceleration in Mobile Devices with Simultaneous Remote Execution.
IEEE Trans. Computers, 2015

Design of configurable I/O pin control block for improving reusability in multimedia SoC platforms.
Multimedia Tools Appl., 2015

Guest Editorial: SBAC-PAD 2013.
International Journal of Parallel Programming, 2015

The Times They Are A-Changin'.
IEEE Computer, 2015

A Performance-Energy Model to Evaluate Single Thread Execution Acceleration.
Computer Architecture Letters, 2015

Performance-energy efficiency model of heterogeneous parallel multicore system.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

How can Garbage Collection be energy efficient by dynamic offloading?
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems.
IEEE Trans. Computers, 2014

Complexity-Effective Contention Management with Dynamic Backoff for Transactional Memory Systems.
IEEE Trans. Computers, 2014

How many cores do we need to run a parallel workload: A test drive of the Intel SCC platform?
J. Parallel Distrib. Comput., 2014

Guest Editorial.
International Journal of Parallel Programming, 2014

Boosting CUDA Applications with CPU-GPU Hybrid Computing.
International Journal of Parallel Programming, 2014

Accelerating MapReduce framework on multi-GPU systems.
Cluster Computing, 2014

An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC.
Computer Architecture Letters, 2014

Fusion Coherence: Scalable Cache Coherence for Heterogeneous Kilo-Core System.
Proceedings of the Advanced Computer Architecture - 10th Annual Conference, 2014

2013
Parallel Sparse Approximate Inverse Preconditioning on Graphic Processing Units.
IEEE Trans. Parallel Distrib. Syst., 2013

Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems.
ACM Trans. Embedded Comput. Syst., 2013

Design and evaluation of random linear network coding Accelerators on FPGAs.
ACM Trans. Embedded Comput. Syst., 2013

Importance of Coherence Protocols with Network Applications on Multicore Processors.
IEEE Trans. Computers, 2013

Acceleration of XML Parsing through Prefetching.
IEEE Trans. Computers, 2013

Practical models for energy-efficient prefetching in mobile embedded systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Pinned OS/Services: A Case Study of XML Parsing on Intel SCC.
J. Comput. Sci. Technol., 2013

Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Mark-Sharing: A Parallel Garbage Collection Algorithm for Low Synchronization Overhead.
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013

Hardware Acceleration for Cryptography Algorithms by Hotspot Detection.
Proceedings of the Grid and Pervasive Computing - 8th International Conference, 2013

Scheduling optimization in multicore multithreaded microprocessors through dynamic modeling.
Proceedings of the Computing Frontiers Conference, 2013

2012
Achieving middleware execution efficiency: hardware-assisted garbage collection operations.
The Journal of Supercomputing, 2012

Minimizing the runtime partial reconfiguration overheads in reconfigurable systems.
The Journal of Supercomputing, 2012

Packer: Parallel Garbage Collection Based on Virtual Spaces.
IEEE Trans. Computers, 2012

Synchronization-Aware Energy Management for VFI-Based Multicore Real-Time Systems.
IEEE Trans. Computers, 2012

Introducing the Extremely Heterogeneous Architecture.
Journal of Interconnection Networks, 2012

Design of Configurable Pin Control Block for Multimedia System-on-a-Chip.
Proceedings of the International Conference on IT Convergence and Security, 2012

Cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids.
Proceedings of the 16th Workshop on Interaction between Compilers and Computer Architectures, 2012

2011
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
IEEE Trans. VLSI Syst., 2011

RHE: A JVM Courseware.
IEEE Trans. Education, 2011

Workload characterization of cryptography algorithms for hardware acceleration (abstracts only).
SIGMETRICS Performance Evaluation Review, 2011

Space-and-Time Efficient Parallel Garbage Collector for Data-Intensive Applications.
International Journal of Parallel Programming, 2011

Value Prediction and Speculative Execution on GPU.
International Journal of Parallel Programming, 2011

Prefetching in Embedded Mobile Systems Can Be Energy-Efficient.
Computer Architecture Letters, 2011

Workload Characterization of Cryptography Algorithms for Hardware Acceleration.
Proceedings of the ICPE'11, 2011

Memory-Side Acceleration for XML Parsing.
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

Keynote talk: Fighting Amdahl's law in many-core and GPU parallel architectures with value prediction.
Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

2010
Network Applications on Simultaneous Multithreading Processors.
IEEE Trans. Computers, 2010

Tolerating Radiation-Induced Transient Faults in Modern Processors.
International Journal of Parallel Programming, 2010

The Performance Analysis and Hardware Acceleration of Crypto-computations for Enhanced Security.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Energy-Efficient Scheduling of Real-Time Periodic Tasks in Multicore Systems.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010

Power Efficient Scheduling for Hard Real-Time Systems on a Multiprocessor Platform.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010

Hardware-assisted security mechanism: The acceleration of cryptographic operations with low hardware cost.
Proceedings of the 29th International Performance Computing and Communications Conference, 2010

Speculative Execution on GPU: An Exploratory Study.
Proceedings of the 39th International Conference on Parallel Processing, 2010

A Theoretical Framework for Value Prediction in Parallel Systems.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Hardware-assisted middleware: Acceleration of garbage collection operations.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

On energy efficiency of reconfigurable systems with run-time partial reconfiguration.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Special issue of Supercomputing Journal on secure, manageable and controllable grid services.
The Journal of Supercomputing, 2009

Potential Impact of Value Prediction on Communication in Many-Core Architectures.
IEEE Trans. Computers, 2009

A complexity-effective microprocessor design with decoupled dispatch queues and prefetching.
Parallel Computing, 2009

Introducing the New Editor-in-Chief of IEEE Computer Architecture Letters.
Computer Architecture Letters, 2009

Packer: An innovative space-time-efficient parallel garbage collection algorithm based on virtual spaces.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

The Impact of Resource Sharing Control on the Design of Multicore Processors.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2009

RHE: A Lightweight JVM Instructional Tool.
Proceedings of the 33rd Annual IEEE International Computer Software and Applications Conference, 2009

Space-and-time efficient garbage collectors for parallel systems.
Proceedings of the 6th Conference on Computing Frontiers, 2009

2008
An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation.
IEEE Trans. Computers, 2008

A low-complexity microprocessor design with speculative pre-execution.
Journal of Systems Architecture - Embedded Systems Design, 2008

Automatic object and image alignment using Fourier Descriptors.
Image Vision Comput., 2008

Design and Implementation of an Agent Home Scheme Strategy for Prefetch-Based DSM Systems.
International Journal of Parallel Programming, 2008

The Impact of Speculative Execution on SMT Processors.
International Journal of Parallel Programming, 2008

A centralized cache miss driven technique to improve processor power dissipation.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Adaptive techniques for leakage power management in L2 cache peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

The potential of fine-grained value prediction in enhancing the performance of modern parallel machines.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

Resource sharing control in Simultaneous MultiThreading microarchitectures.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
Architectural Implications of Cache Coherence Protocols with Network Applications on Chip MultiProcessors.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007

Architectural Support for Network Applications on Simultaneous MultiThreading Processors.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Synchronization Mechanisms on Modern Multi-core Architectures.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Design and evaluation of a hierarchical decoupled architecture.
The Journal of Supercomputing, 2006

Throttling-Based Resource Management in High Performance Multithreaded Architectures.
IEEE Trans. Computers, 2006

A Simple High-Speed Multiplier Design.
IEEE Trans. Computers, 2006

A Multithreaded Sql Service.
Parallel Processing Letters, 2006

Adaptive dynamic thread scheduling for simultaneous multithreaded architectures with a detector thread.
J. Parallel Distrib. Comput., 2006

Speculative pre-execution assisted by compiler (SPEAR).
J. Parallel Distrib. Comput., 2006

Introduction.
J. Parallel Distrib. Comput., 2006

Foreword.
Computer Architecture Letters, 2006

A Wiki for discussing and promoting best practices in research.
Commun. ACM, 2006

Design Trade-Offs and Deadlock Prevention in Transient Fault-Tolerant SMT Processors.
Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Features of Future Network Processor Architectures.
Proceedings of the 2006 IEEE John Vincent Atanasoff International Symposium on Modern Computing (JVA2006), 2006

The Walls of Computer Design.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Low Power Microprocessor Design for Embedded Systems.
Proceedings of the Computational Science and Its Applications, 2006

Design and Effectiveness of Small-Sized Decoupled Dispatch Queues.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
Area and System Clock Effects on SMT/CMP Throughput.
IEEE Trans. Computers, 2005

Automatic Array Partitioning Based on the Smith Normal Form.
International Journal of Parallel Programming, 2005

Message from the Guest Editors.
International Journal of Parallel Programming, 2005

Foreword (Special Issue on Applications for High-Performance Systems).
IJCAT, 2005

Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW.
Advances in Computers, 2005

A Logarithmic Time Method for Two's Complementation.
Proceedings of the Computational Science, 2005

A Low-Complexity Issue Queue Design with Speculative Pre-execution.
Proceedings of the High Performance Computing, 2005

Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures.
Proceedings of the Advanced Parallel Processing Technologies, 6th InternationalWorkshop, 2005

2004
The need for adaptive dynamic thread scheduling in simultaneous multithreading.
Parallel Processing Letters, 2004

Alias Analysis in Java with Reference-Set Representation for High-Performance Computing.
International Journal of Parallel Programming, 2004

On Design of Cluster and Grid Computing Environment Toolkit for Bioinformatics Applications.
Proceedings of the Distributed Computing, 2004

SPEAR: A Hybrid Model for Speculative Pre-Execution.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Speculation Control for Simultaneous Multithreading.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations.
Proceedings of the Implementation and Application of Functional Languages, 2004

A Fast and Well-Structured Multiplier.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture.
Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004

A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003
Introducing the New Editor-in-Chief of the IEEE Transactions on Computers.
IEEE Trans. Computers, 2003

Non-Strict Execution in Parallel and Distributed Computing.
International Journal of Parallel Programming, 2003

Incomplete Information Processing for Optimization of Distributed Applications.
Proceedings of the ACIS Fourth International Conference on Software Engineering, 2003

Non-strict Evaluation of the FFT Algorithm in Distributed Memory Systems.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface,10th European PVM/MPI Users' Group Meeting, Venice, Italy, September 29, 2003

Modeling and Predicting Point-to-Point Communications of MPI Parallel Programs in NOW Environments.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Dynamic Scheduling Issues in SMT Architectures.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

HiDISC: A Decoupled Architecture for Data-Intensive Application.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Clustered Microarchitecture Simultaneous Multithreading.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Compiler Support for Dynamic Speculative Pre-Execution.
Proceedings of the 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 2003

2002
SMT Layout Overhead and Scalability.
IEEE Trans. Parallel Distrib. Syst., 2002

Editor's Note.
IEEE Trans. Computers, 2002

Editor's Note.
IEEE Trans. Computers, 2002

Editor's Note.
IEEE Trans. Computers, 2002

On a scheme for parallel sorting on heterogeneous clusters.
Future Generation Comp. Syst., 2002

Performance Prediction Methodology for Parallel Programs with MPI in NOW Environments.
Proceedings of the Distributed Computing, 2002

An Evaluation of Thread Migration for Exploiting Distributed Array Locality.
Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

Parallel Computer Architecture and Instruction-Level Parallelism.
Proceedings of the Euro-Par 2002, 2002

Alias Analysis for Exceptions in Java.
Proceedings of the Computer Science 2002, 2002

2001
Editor's Note.
IEEE Trans. Computers, 2001

Editorial Note.
Parallel Processing Letters, 2001

Benchmarking Clusters of Workstations Through Parallel Sorting and BSP Libraries.
Parallel Processing Letters, 2001

Enhancing Functional and Irregular Parallelism: Stateful Functions and their Semantics.
International Journal of Parallel Programming, 2001

Exploiting Locality in Single Assignment Data Structures Updated Through Split-Phase Transactions.
Cluster Computing, 2001

Alias Analysis for Java with Reference-Set Representation.
Proceedings of the Eigth International Conference on Parallel and Distributed Systems, 2001

MCOMA: A Multithreaded COMA Architecture.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

The Sisal Project: Real World Functional Programming.
Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

Alias Analysis On Type Inference For Class Hierarchy In Java.
Proceedings of the 24th Australasian Computer Science Conference (ACSC 2001), 29 January, 2001

Area and System Clock Effects on SMT/CMP Processors.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
Editor's Note.
IEEE Trans. Computers, 2000

Editor's Note.
IEEE Trans. Computers, 2000

Editor's Note.
IEEE Trans. Computers, 2000

An efficient heuristic for code partitioning.
Parallel Computing, 2000

Flat Indexing Scheme: A New Compilation Technique to Enhance Parallelism of Logic Programs.
J. Inf. Sci. Eng., 2000

Caching Single-Assignment Structures to Build a Robust Fine-Grain Multi-Threading System.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Parallel Sorting Algorithms with Sampling Techniques on Clusters with Processors Running at Different Speeds.
Proceedings of the High Performance Computing, 2000

An Over-partitioning Scheme for Parallel Sorting on Clusters with Processors Running at different Speeds.
Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

1999
Communication Generation for Aligned and Cyclic(K) Distributions Using Integer Lattice.
IEEE Trans. Parallel Distrib. Syst., 1999

Algorithms for Stable Sorting to Minimize Communications in Networks of Workstations and Their Implementations in BSP.
Proceedings of the 1st International Workshop on Cluster Computing (IWCC '99), 1999

1998
Analysis of a Heuristic for Code Partitioning.
The Journal of Supercomputing, 1998

Implementing Parallel Branch-and-Bound with Extended Sisal 2.0.
Parallel Processing Letters, 1998

Flat Indexing: A Compilation Technique to Enhance Parallelism of Logic Programs.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

1997
Data and Workload Distribution in a Multithreaded Architecture.
J. Parallel Distrib. Comput., 1997

Exploiting locality and tolerating remote memory access latency using thread migration.
International Journal of Parallel Programming, 1997

Exploiting Global Data Locality in Non-Blocking Multithreaded Architectures.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Two Techniques for Static Array Partitioning on Message-Passing Parallel Machines.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996
Parallel Computing with the Sisal Applicative Language: Programmability and Performance Issues.
Softw., Pract. Exper., 1996

Guest Editor's Introduction.
International Journal of Parallel Programming, 1996

Extending functional languages with stateful computations.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

An Application of Extended Sisal 2.0.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Effects of Multithreading on Data and Workload Distribution for Distributed-Memory Multiprocessors.
Proceedings of IPPS '96, 1996

A Scalable Cache Design for I-Structures in Multithreaded Architectures.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

Worker-Based Parallel Computing on PVM.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

I-Structure Software Cache: a split-phase transaction runtime cache system.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

Nomadic Threads: a migrating multithreaded approach to remote memory accesses in multiprocessors.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Implementing regularly structured neural networks on the DREAM machine.
IEEE Trans. Neural Networks, 1995

Incorporating Input/Output Operations Into Dynamic Data-Flow Graphs.
Parallel Computing, 1995

Advanced topics in dataflow computing and multithreading.
IEEE, ISBN: 978-0-8186-6542-4, 1995

1994
Authors' Reply.
IEEE Trans. Computers, 1994

Distributed parallel object-oriented environment for traffic simulation (POETS).
Proceedings of the 26th conference on Winter simulation, 1994

A Hierarchical Activation Management Technique for Fine-Grain Multithreaded Execution.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

A Direct Array Injection Technique in a Fine-Grain Multithreading Execution Model.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel Architectures.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1993
Block Scheduling of Iterative Algorithms and Graph-Level Priority Scheduling in a Simulated Data-Flow Multiprocessor.
IEEE Trans. Parallel Distrib. Syst., 1993

Special Issue on DataFlow and Multithreaded Architectures - Guest Editors' Introduction.
J. Parallel Distrib. Comput., 1993

Parallel Implementations of Neural Networks.
International Journal on Artificial Intelligence Tools, 1993

Data-Driven Execution of Logic Languages.
Proceedings of the ICLP'93 Post Conference Workshop on: Concurrent, 1993

1992
A Survey on the Parallel Distributed Processing of Production Systems.
International Journal on Artificial Intelligence Tools, 1992

Parallelism Profiling of an Ops5 Production System Interpreter.
Proceedings of the SEKE'92, 1992

Performance Evaluation of the Multiple Root Node Approach to the Rete Pattern Matcher for Production Systems.
FGCS, 1992

1991
Chaotic Linear System Solvers in a Variable-Grain Data-Driven Multiprocessor System.
Proceedings of the PARLE '91: Parallel Architectures and Languages Europe, 1991

Input/Output Operations for Hybrid Data-Flow/Control-Flow Systems.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

A Macro Actor/Token Implementation of Production Systems on a Data-Mow Multiprocessor.
Proceedings of the 12th International Joint Conference on Artificial Intelligence. Sydney, 1991

A scheme to extract run-time parallelism form sequential loops.
Proceedings of the 5th international conference on Supercomputing, 1991

1990
Data-Driven Parallel Production Systems.
IEEE Trans. Software Eng., 1990

Network Resilience: A Measure of Network Fault Tolerance.
IEEE Trans. Computers, 1990

Network design and allocation considerations in the Hughes data-flow machine.
Parallel Computing, 1990

Special Issue on Data-Flow Computing: Guest Editors' Introduction.
J. Parallel Distrib. Comput., 1990

Representing and Processing Production Systems in Connectionist Architectures.
IJPRAI, 1990

Distributed input/output processing in data-driven multiprocessors.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

A data-driven execution paradigm for distributed fault-tolerance.
Proceedings of the 4th ACM SIGOPS European Workshop, Bologna, Italy, September 3-5, 1990, 1990

A connectionist approach to learning legal moves in Tower-of-Hanoi.
Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence, 1990

Compiling Programs to Direct Access Data-Flow Graphs.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

A Decoupled Graph/Computation Data-Driven Architecture with Variable-Resolution Actors.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

A Decoupled Data-Driven Architecture with Vectors and Macro Actors.
Proceedings of the CONPAR 90, 1990

Data-driven approach for programming a transputer-based system.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1989
Token Relabeling in a Tagged Token Data-Flow Architecure.
IEEE Trans. Computers, 1989

Occamflow: A Methodology for Programming Multiprocessor Systems.
J. Parallel Distrib. Comput., 1989

Limits on Scalability in Gracefully Degradable Large-Scale Systems.
Proceedings of the Eigthth Symposium on Reliable Distributed Systems, 1989

A Single-Assignment Language in a Distributed Memory Multiprocessor.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

Multilayer of ring-structured feedback network for production system processing.
Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989

Parallel Computing: One Opportunity, Four Challenges.
Proceedings of the Fifth International Conference on Data Engineering, 1989

1988
Demand-Driven Interpretation of FP Programs on a Data-Flow Multiprocessor.
IEEE Trans. Computers, 1988

Program graph allocation in distributed multicomputers.
Parallel Computing, 1988

Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment.
Proceedings of the 15th Annual International Symposium on Computer Architecture. Honolulu, 1988

Data-Driven Multiprocessor Implementation of the Rete Match Algorithm.
Proceedings of the International Conference on Parallel Processing, 1988

Iterative Algorithms in a Data-Driven Environment.
Proceedings of the International Conference on Parallel Processing, 1988

Network Disconnection in Distributed Systems.
Proceedings of the 8th International Conference on Distributed Computing Systems, 1988

Lazy Evaluation of FP Programs: A Data-Flow Approach.
FGCS, 1988

1987
Multiprocessor Systems Programming in a High-Level Data-Flow Language.
Proceedings of the PARLE, 1987

Reliability and Performance Modelling of Hypercube-Based Mutliprocessors.
Proceedings of the Computer Performance and Reliability, 1987

Multi-Level Execution In Data-Flow Architectures.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Structure Handling in Data-Flow Systems.
IEEE Trans. Computers, 1986

An eclectic 5th generation architecture for ultra high speed computing.
SIGART Newsletter, 1986

The TX16: A Highly Programmable Multi-microprocessor Architecture.
IEEE Micro, 1986

: Token Relabeling in a Tagged Data-Flow Architecture.
Proceedings of the International Conference on Parallel Processing, 1986

1985
A Distributed VLSI Architecture for Efficient Signal and Data Processing.
IEEE Trans. Computers, 1985

Performance evaluation of a simulated data-flow computer with low-resolution actors.
J. Parallel Distrib. Comput., 1985

Methods for Handling Structures in Data-Flow Systems.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

Fault-Tolerance and Data-Flow Systems.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985

1984
Performance Analysis of a Data-Flow Computer with Variable Resolution Actors.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

1982
A scheme for handling arrays in data-flow systems.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982


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