Mitrajit Chatterjee

According to our database1, Mitrajit Chatterjee authored at least 10 papers between 1993 and 2003.

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Bibliography

2003
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
IEEE Trans. Computers, 2003

2000
VERILAT: verification using logic augmentation and transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers, 2000

1999
GLFSR-a new test pattern generator for built-in-self-test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1996
Gate-level synthesis for low-power using new transformations.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

BIT-based weighted mean filter.
Proceedings of the 8th European Signal Processing Conference, 1996

1995
A novel pattern generator for near-perfect fault-coverage.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

LOT: logic optimization with testability-new transformations using recursive learning.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1993
Buffer assignment for data driven architectures.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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