Dhiraj K. Pradhan
Affiliations:- University of Bristol, UK
According to our database1,
Dhiraj K. Pradhan
authored at least 266 papers
between 1972 and 2021.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 1999, "For contributions to VLSI CAD test, and Fault-tolerant Systems Design, including leadership in computer engineering, and computer science education and research.".
Timeline
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Bibliography
2021
2017
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.
IEEE Trans. Reliab., 2017
ACM Trans. Embed. Comput. Syst., 2017
2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2015
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab., 2015
ACM Trans. Embed. Comput. Syst., 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron., 2014
J. Low Power Electron., 2014
Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett., 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
A placement strategy for reducing the effects of multiple faults in digital circuits.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
A hybrid reliability assessment method and its support of sequential logic modelling.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Complementary resistive switch based stateful logic operations using material implication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng., 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.
J. Low Power Electron., 2012
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.
Integr., 2012
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab., 2011
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electron., 2011
Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks.
Int. J. Sens. Networks, 2011
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
J. Low Power Electron., 2010
ULS: A dual-<i>V<sub>th</sub></i>/high-kappa nano-CMOS universal level shifter for system-level power management.
ACM J. Emerg. Technol. Comput. Syst., 2010
ACM J. Emerg. Technol. Comput. Syst., 2010
Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010
IET Comput. Digit. Tech., 2010
Comput. J., 2010
Proceedings of the Recent Trends in Wireless and Mobile Networks, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the Eigth Annual IEEE International Conference on Pervasive Computing and Communications, 2010
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors.
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Improving reliability for bit parallel finite field multipliers using Decimal Hamming.
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V<sub><i>DD</i></sub> applications.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
An O(m<sup>2</sup>)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2<sup>m</sup>)<sup>a</sup>.
Quantum Inf. Comput., 2009
IET Comput. Digit. Tech., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
ACM Trans. Design Autom. Electr. Syst., 2008
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
GfXpress: A Technique for Synthesis and Optimization of GF(2<sup>m</sup>) Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Computers, 2008
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.
IET Comput. Digit. Tech., 2008
Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Electron. Express, 2008
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography.
Proceedings of the Theory of Quantum Computation, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008
Proceedings of the 5th Conference on Computing Frontiers, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers, 2007
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers, 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 10th International Conference on Information Technology, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
An efficient technique for synthesis and optimization of polynomials in GF(2<sup><i>m</i></sup>).
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
LPRAM: a novel low-power high-performance RAM design with testability and scalability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances.
Proceedings of the SAT 2004, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Computers, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Mathematical framework for representing discrete functions as word-level polynomials.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the 2003 Design, 2003
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
1997
IEEE Trans. Computers, 1997
Proceedings of the 17th International Conference on Distributed Computing Systems, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.
IEEE Trans. Computers, 1996
Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability.
J. Parallel Distributed Comput., 1996
Comput. Commun., 1996
Comput. Commun., 1996
Proceedings of the Proceedings 21st Conference on Local Computer Networks, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the Digest of Papers: FTCS-26, 1996
Proceedings of the 8th European Signal Processing Conference, 1996
1995
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation.
IEEE Trans. Parallel Distributed Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Computers, 1995
Computer, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 2nd Symposium on Mobile and Location-Independent Computing (MLICS'95), 1995
LOT: logic optimization with testability-new transformations using recursive learning.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
Proceedings of the 32st Conference on Design Automation, 1995
1994
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Computers, 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Third International Conference on Parallel and Distributed Information Systems (PDIS 94), 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Trans. Parallel Distributed Syst., 1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
IEEE Trans. Computers, 1993
A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the Seventh International Parallel Processing Symposium, 1993
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the 13th International Conference on Distributed Computing Systems, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the Hardware and Software Architectures for Fault Tolerance, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, 1992
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the 6th International Parallel Processing Symposium, 1992
1991
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression.
IEEE Trans. Computers, 1991
SIGARCH Comput. Archit. News, 1991
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991
Proceedings of the Proceedings Supercomputing '91, 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the 10th International Conference on Distributed Computing Systems (ICDCS 1991), 1991
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
1990
IEEE Trans. Computers, 1990
IEEE Trans. Computers, 1990
Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems.
Proceedings of the 1990 International Conference on Parallel Processing, 1990
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
Proceedings of the Application Specific Array Processors, 1990
1989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI.
IEEE Trans. Computers, 1989
SIGARCH Comput. Archit. News, 1989
Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties).
Proceedings of the Reliability Of Computer And Communication Networks, 1989
1988
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers, 1988
Proceedings of the Proceedings International Test Conference 1988, 1988
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability.
Proceedings of the Proceedings International Test Conference 1988, 1988
1987
IEEE Trans. Computers, 1987
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987
1986
Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems.
Proc. IEEE, 1986
1985
IEEE Trans. Computers, 1985
IEEE Trans. Computers, 1985
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985
1984
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984
1983
IEEE Trans. Computers, 1983
1982
IEEE Trans. Computers, 1982
On a Class of Fault-Tolerant Multiprocessor Network Architectures.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982
1981
Completely Self-Checking Checkers in PLAs.
Proceedings of the Proceedings International Test Conference 1981, 1981
1980
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines.
IEEE Trans. Computers, 1980
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications.
IEEE Trans. Computers, 1980
IEEE Trans. Computers, 1980
1978
IEEE Trans. Computers, 1978
IEEE Trans. Computers, 1978
IEEE Trans. Computers, 1978
1977
IEEE Trans. Computers, 1977
Inf. Sci., 1977
1976
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers, 1976
1975
IEEE Trans. Computers, 1975
1974
1973
1972