Dhiraj K. Pradhan

According to our database1, Dhiraj K. Pradhan authored at least 255 papers between 1972 and 2017.

Collaborative distances:
  • Dijkstra number2 of three.
  • Erdős number3 of two.

Awards

ACM Fellow

ACM Fellow 1999, "For contributions to VLSI CAD test, and Fault-tolerant Systems Design, including leadership in computer engineering, and computer science education and research.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2017
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.
IEEE Trans. Reliab., 2017

Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing".
ACM Trans. Embed. Comput. Syst., 2017

Selected Articles from the IEEE ISED 2016 Conference.
J. Low Power Electron., 2017

2016
Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab., 2015

A Novel Memristor-Based Hardware Security Primitive.
ACM Trans. Embed. Comput. Syst., 2015

Selected Articles from the IEEE ISED 2014 Conference.
J. Low Power Electron., 2015

A novel memristor based physically unclonable function.
Integr., 2015

2T2M memristor based TCAM cell for low power applications.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Fault detection and repair of DSC arrays through memristor sensing.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron., 2014

Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System.
J. Low Power Electron., 2014

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett., 2014

Write scheme for multiple Complementary Resistive Switch (CRS) cells.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

A placement strategy for reducing the effects of multiple faults in digital circuits.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A hybrid reliability assessment method and its support of sequential logic modelling.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Using memristor state change behavior to identify faults in photovoltaic arrays.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Complementary resistive switch based stateful logic operations using material implication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


2013
DeSyRe: On-demand system reliability.
Microprocess. Microsystems, 2013

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng., 2013

Low Power and Robust Binary Tree SRAM Design for Embedded Systems.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Multinomial Memristor Model for Simulations and Analysis.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Software Modification Aided Transient Error Tolerance for Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A fast and Effective DFT for test and diagnosis of power switches in SoCs.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.
J. Low Power Electron., 2012

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.
Integr., 2012

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

STEP: a unified design methodology for secure test and IP core protection.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

The DeSyRe Project: On-Demand System Reliability.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Routing-Aware ILS Design Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Matrix Codes for Reliable and Cost Efficient Memory Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab., 2011

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electron., 2011

Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks.
Int. J. Sens. Networks, 2011

Fault Tolerant Single Error Correction Encoders.
J. Electron. Test., 2011

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process., 2011

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

BCH code based multiple bit error correction in finite field multiplier circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

Single-Event Transient Analysis in High Speed Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Test Generation in Systolic Architecture for Multiplication Over GF(2 <sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010

DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.
J. Low Power Electron., 2010

ULS: A dual-<i>V<sub>th</sub></i>/high-kappa nano-CMOS universal level shifter for system-level power management.
ACM J. Emerg. Technol. Comput. Syst., 2010

Introduction to design techniques for energy harvesting.
ACM J. Emerg. Technol. Comput. Syst., 2010

Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010

A Galois field-based logic synthesis with testability.
IET Comput. Digit. Tech., 2010

Secure Testable S-box Architecture for Cryptographic Hardware Implementation.
Comput. J., 2010

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

On the synthesis of attack tolerant cryptographic hardware.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fault diagnosis in multi layered De Bruijn based architectures for sensor networks.
Proceedings of the Eigth Annual IEEE International Conference on Pervasive Computing and Communications, 2010

Improved Yield in Nanotechnology Circuits Using Non-square Meshes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

On the design of different concurrent EDC schemes for S-Box and GF(p).
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Layout-aware Illinois Scan design for high fault coverage coverage.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Improving reliability for bit parallel finite field multipliers using Decimal Hamming.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Investigating the impact of NBTI on different power saving cache strategies.
Proceedings of the Design, Automation and Test in Europe, 2010

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V<sub><i>DD</i></sub> applications.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
An O(m<sup>2</sup>)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2<sup>m</sup>)<sup>a</sup>.
Quantum Inf. Comput., 2009

Single error correctable bit parallel multipliers over GF(2<sup>m</sup>).
IET Comput. Digit. Tech., 2009

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Reliability aware yield improvement technique for nanotechnology based circuits.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Increasing memory yield in future technologies through innovative design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

C-testable S-box implementation for secure advanced encryption standard.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A fast error correction technique for matrix multiplication algorithms.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Single ended 6T SRAM with isolated read-port for low-power embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Fault-Tolerant Computing.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

C-testable bit parallel multipliers over <i>GF</i>(2<sup><i>m</i></sup>).
ACM Trans. Design Autom. Electr. Syst., 2008

Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

GfXpress: A Technique for Synthesis and Optimization of GF(2<sup>m</sup>) Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers, 2008

Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.
IET Comput. Digit. Tech., 2008

Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A single ended 6T SRAM cell design for ultra-low-voltage applications.
IEICE Electron. Express, 2008

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Galois Field Based Logic Synthesis Approach with Testability.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Single Error Correcting Finite Field Multipliers Over GF(2m).
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography.
Proceedings of the Theory of Quantum Computation, 2008

Pseudo parallel architecture for AES with error correction.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Failure analysis for ultra low power nano-CMOS SRAM under process variations.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Area Reliability Trade-Off in Improved Reed Muller Coding.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A nano-CMOS process variation induced read failure tolerant SRAM cell.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault tolerant bit parallel finite field multipliers using LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault Tolerant Reversible Finite Field Arithmetic Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

Multiple Event Upsets Aware FPGAs Using Protected Schemes.
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008

2007
A Defect Tolerance Scheme for Nanotechnology Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers, 2007

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers, 2007

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Improved decoding algorithm for high reliable reed muller coding.
Proceedings of the 2007 IEEE International SOC Conference, 2007

High defect tolerant low cost memory chips.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A soft error robust and power aware memory design.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Multiple Upsets Tolerance in SRAM Memory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Highly Reliable Power Aware Memory Design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Reliable network-on-chip based on generalized de Bruijn graph.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Single Event Upset Detection and Correction.
Proceedings of the 10th International Conference on Information Technology, 2007

2006
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

An efficient technique for synthesis and optimization of polynomials in GF(2<sup><i>m</i></sup>).
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m).
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Reuse-based test access and integrated test scheduling for network-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
EBIST: a novel test generator with built-in fault detection capability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Recent Advances in Verification, Equivalence Checking and SAT-Solvers.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Comparative study of CA with phase shifters and GLFSRs.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

GASIM: a fast Galois field based simulator for functional model.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
LPRAM: a novel low-power high-performance RAM design with testability and scalability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances.
Proceedings of the SAT 2004, 2004

Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

MODD for CF: a representation for fast evaluation of multiple-output functions.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
Proceedings of the 2004 Design, 2004

LPRAM: a low power DRAM with testability.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
IEEE Trans. Computers, 2003

Wormhole routing in de Bruijn networks and hyper-de Bruijn networks.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Mathematical framework for representing discrete functions as word-level polynomials.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Logic transformation and coding theory-based frameworks for Boolean satisfiability.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

EBIST: A Novel Test Generator with Built-In Fault Detection Capability.
Proceedings of the 2003 Design, 2003

2001
ATPG for Design Errors-Is It Possible?
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Logic Insertion to Speed-Up Logic Verification: A Recent Development.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

2000
VERILAT: verification using logic augmentation and transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers, 2000

1999
GLFSR-a new test pattern generator for built-in-self-test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
Job Scheduling in Mesh Multicomputers.
IEEE Trans. Parallel Distributed Syst., 1998

LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off.
IEEE Trans. Computers, 1997

A cluster-based approach for routing in dynamic networks.
Comput. Commun. Rev., 1997

Improving Performance of TCP over Wireless Networks.
Proceedings of the 17th International Conference on Distributed Computing Systems, 1997

1996
Synthesis of initializable asynchronous circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1996

A novel framework for logic verification in a synthesis environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.
IEEE Trans. Computers, 1996

The Effect of Program Behavior on Fault Observability.
IEEE Trans. Computers, 1996

Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability.
J. Parallel Distributed Comput., 1996

Static and adaptive location management in mobile wireless networks.
Comput. Commun., 1996

Modified tree structure for location management in mobile environments.
Comput. Commun., 1996

Providing Seamless Communication in Mobile Wireless Networks.
Proceedings of the Proceedings 21st Conference on Local Computer Networks, 1996

Gate-level synthesis for low-power using new transformations.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Sequential redundancy identification using recursive learning.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Recoverable Mobile Environment: Design and Trade-Off Analysis.
Proceedings of the Digest of Papers: FTCS-26, 1996

BIT-based weighted mean filter.
Proceedings of the 8th European Signal Processing Conference, 1996

1995
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation.
IEEE Trans. Parallel Distributed Syst., 1995

A novel scheme to reduce test application time in circuits with full scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms.
IEEE Trans. Computers, 1995

Fault Injection: A Method for Validating Computer-System Dependability.
Computer, 1995

A novel pattern generator for near-perfect fault-coverage.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Cluster-based Approach for Routing in Ad-Hoc Networks.
Proceedings of the 2nd Symposium on Mobile and Location-Independent Computing (MLICS'95), 1995

LOT: logic optimization with testability-new transformations using recursive learning.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Safe System Level Diagnosis.
IEEE Trans. Computers, 1994

Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture.
IEEE Trans. Computers, 1994

Functional learning: a new approach to learning in digital circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Location Management in Distributed Mobile Environments.
Proceedings of the Third International Conference on Parallel and Distributed Information Systems (PDIS 94), 1994

Bit-Serial Generalized Median Filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Subcube Level Time-Sharing in Hypercube Multicomputers.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Recovery in Multicomputers with Finite Error Detection Latency.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Initialization Isuues in the Synthesis of Asynchronous Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Signal Transition Graph Transformations for Initializability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A new algorithm for order statistic and sorting.
IEEE Trans. Signal Process., 1993

The Hyper-deBruijn Networks: Scalable Versatile Architecture.
IEEE Trans. Parallel Distributed Syst., 1993

Accelerated dynamic learning for test pattern generation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Fault-Tolerant Design Strategies for High Reliability and Safety.
IEEE Trans. Computers, 1993

Modeling Live and Dead Lines in Cache Memory Systems.
IEEE Trans. Computers, 1993

Communication structures in fault-tolerant distributed systems.
Networks, 1993

Processor- and Memory-Based Checkpoint and Rollback Recovery.
Computer, 1993

A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Scalability of Binary deBruijn Networks.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Degradable Agreement in the Presence of Byzantine Faults.
Proceedings of the 13th International Conference on Distributed Computing Systems, 1993

Desgin for Testability of Asynchronous Sequential Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Buffer assignment for data driven architectures.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Roll-Forward Checkpointing Schemes.
Proceedings of the Hardware and Software Architectures for Fault Tolerance, 1993

An application specific processor for implementing stack filters.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
A new class of bit- and byte-error control codes.
IEEE Trans. Inf. Theory, 1992

Virtual Checkpoints: Architecture and Performance.
IEEE Trans. Computers, 1992

A design for testability scheme to reduce test application time in full scan.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

A Novel Approach for Subcube Allocation in Hypercube Multiprocessors.
Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, 1992

Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Can Concurrent Checkers Help BIST?
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors.
Proceedings of the 6th International Parallel Processing Symposium, 1992

1991
Consensus With Dual Failure Modes.
IEEE Trans. Parallel Distributed Syst., 1991

A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression.
IEEE Trans. Computers, 1991

Two economical directory schemes for large-scale cache coherent multiprocessors.
SIGARCH Comput. Archit. News, 1991

BDG-torus union graph-an efficient algorithmically specializedparallel interconnect.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

A virtual memory translation mechanism to support checkpoint and rollback recovery.
Proceedings of the Proceedings Supercomputing '91, 1991

Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

The hyper-deBruijn multiprocessor networks.
Proceedings of the 10th International Conference on Distributed Computing Systems (ICDCS 1991), 1991

System Level Diagnosis: Combining Detection and Location.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

Program Fault Tolerance Based on Memory Access Behavior.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990
Aliasing Probability for Multiple Input Signature Analyzer.
IEEE Trans. Computers, 1990

Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers, 1990

Error-Control Coding in Computers.
Computer, 1990

Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

Zero aliasing compression.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

Application specific VLSI architectures based on De Bruijn graphs.
Proceedings of the Application Specific Array Processors, 1990

1989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI.
IEEE Trans. Computers, 1989

Modeling Defect Spatial Distribution.
IEEE Trans. Computers, 1989

Dynamic Testing Strategy for Distributed Systems.
IEEE Trans. Computers, 1989

Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties).
Proceedings of the Reliability Of Computer And Communication Networks, 1989

1988
Flip-Trees: Fault-Tolerant Graphs with Wide Containers.
IEEE Trans. Computers, 1988

TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers, 1988

RTRAM: Reconfigurable and Testable Multi-Bit RAM Design.
Proceedings of the Proceedings International Test Conference 1988, 1988

A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability.
Proceedings of the Proceedings International Test Conference 1988, 1988

1987
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems.
IEEE Trans. Computers, 1987

Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1985
Dynamically Restructurable Fault-Tolerant Processor Network Architectures.
IEEE Trans. Computers, 1985

Fault-Tolerant Multiprocessor Link and Bus Network Architectures.
IEEE Trans. Computers, 1985

The de Bruijn Multiprocessor Network: A Versatile Sorting Network.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1983
Sequential Network Design Using Extra Inputs for Fault Detection.
IEEE Trans. Computers, 1983

1982
A Fault-Tolerant Communication Architecture for Distributed Systems.
IEEE Trans. Computers, 1982

Optimal Unidirectional Error Detecting/Correcting Codes.
IEEE Trans. Computers, 1982

On a Class of Fault-Tolerant Multiprocessor Network Architectures.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982

1981
Completely Self-Checking Checkers in PLAs.
Proceedings of the Proceedings International Test Conference 1981, 1981

1980
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines.
IEEE Trans. Computers, 1980

A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications.
IEEE Trans. Computers, 1980

Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets.
IEEE Trans. Computers, 1980

Error-Correcting Codes and Self-Checking Circuits.
Computer, 1980

Fault-Tolerant Computing.
Computer, 1980

1978
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design.
IEEE Trans. Computers, 1978

A Theory of Galois Switching Functions.
IEEE Trans. Computers, 1978

Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays.
IEEE Trans. Computers, 1978

Fault-Tolerant Asynchronous Networks Using Read-Only Memories.
IEEE Trans. Computers, 1978

1977
Store Address Generator with On-Line Fault-Detection Capability.
IEEE Trans. Computers, 1977

A graph-structural approach for the generalization of data management systems.
Inf. Sci., 1977

1976
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers, 1976

1975
Reed-Muller Like Canonic Forms for Multivalued Functions.
IEEE Trans. Computers, 1975

1974
Design of Two-Level Fault-Tolerant Networks.
IEEE Trans. Computers, 1974

1973
Fault-Tolerant Asynchronous Networks.
IEEE Trans. Computers, 1973

1972
Error-Control Techniques for Logic Processors.
IEEE Trans. Computers, 1972


  Loading...