Savita Banerjee

According to our database1, Savita Banerjee authored at least 9 papers between 1993 and 2010.

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Bibliography

2010
On the synthesis of attack tolerant cryptographic hardware.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Layout-aware Illinois Scan design for high fault coverage coverage.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2000
Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers, 2000

1996
Synthesis of initializable asynchronous circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Initialization issues in asynchronous circuit synthesis.
J. Electron. Test., 1996

Synchronous Test Generation Model for Asynchronous Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994
Initialization Isuues in the Synthesis of Asynchronous Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Signal Transition Graph Transformations for Initializability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Buffer assignment for data driven architectures.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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