Mohammadreza Esmaeilpour

According to our database1, Mohammadreza Esmaeilpour authored at least 8 papers between 2024 and 2025.

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Bibliography

2025
Enhanced LPDDR4X PHY in 12 nm FinFET.
CoRR, March, 2025

A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique.
Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables.
Proceedings of the 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2025

2024
A Wide-Range Low-Power Phase Interpolation-Based Delay Line with a Linearity Improvement Technique.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design - 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024


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