Jan Lappas

According to our database1, Jan Lappas authored at least 9 papers between 2019 and 2022.

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Bibliography

2022
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.
Proceedings of the IEEE European Test Symposium, 2022

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.
J. Signal Process. Syst., 2021

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Efficient Hardware Architectures for 1D- and MD-LSTM Networks.
J. Signal Process. Syst., 2020

2019
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

An In-DRAM Neural Network Processing Engine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019


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