Jan Lappas

According to our database, Jan Lappas authored at least 20 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization.

Mohsen Ahmadzadeh, Jan Lappas, Norbert Wehn, Georges G. E. Gielen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2026

2025

Enhanced LPDDR4X PHY in 12 nm FinFET.

Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Hussien Abdo, Christian Weis, Norbert Wehn

CoRR, March, 2025

A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology.

Marco Mestice, Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn

Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique.

Mohammadreza Esmaeilpour, Marco Mestice, Jan Lappas, Christian Weis, Norbert Wehn

Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables.

Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn

Proceedings of the 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2025

2024

A Wide-Range Low-Power Phase Interpolation-Based Delay Line with a Linearity Improvement Technique.

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design - 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology.

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces.

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces.

Mohammadreza Esmaeilpour, Jan Lappas, Hussien Abdo, Christian Weis, Norbert Wehn

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Timing Analysis with Analytical Sensitivity.

Jan Lappas, Norbert Wehn, Sani R. Nassif

Proceedings of the 21st International SoC Design Conference, 2024

Timing Analysis beyond Complementary CMOS Logic Styles.

Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2022

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.

André Lucas Chinazzo, Jan Lappas, Christian Weis, Qinhui Huang, Zhihang Wu, Leibin Ni, Norbert Wehn

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.

Zhe Zhang, Jan Lappas, André Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni, Norbert Wehn, Mehdi B. Tahoori

Proceedings of the IEEE European Test Symposium, 2022

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.

Jan Lappas, André Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng

J. Signal Process. Syst., 2021

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.

Chirag Sudarshan, Lukas Steiner, Matthias Jung, Jan Lappas, Christian Weis, Norbert Wehn

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng

J. Signal Process. Syst., 2020

2019

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

An In-DRAM Neural Network Processing Engine.

Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019