Norbert Wehn

According to our database1, Norbert Wehn authored at least 224 papers between 1986 and 2019.

Collaborative distances:
  • Dijkstra number2 of three.
  • Erdős number3 of two.

Timeline

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Bibliography

2019
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.
CoRR, 2019

A Reduced-Complexity Projection Algorithm for ADMM-based LP Decoding.
CoRR, 2019

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Adaptive Transient Computing for Power-Neutral Embedded Devices.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Fast validation of DRAM protocols with timed petri nets.
Proceedings of the International Symposium on Memory Systems, 2019

An In-DRAM Neural Network Processing Engine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Polar Code Decoder Framework.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Speculative Temporal Decoupling Using fork().
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Low-Latency CRC Calculation in Turbo-Code Decoding.
IJWIN, 2018

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs.
IEEE Design & Test, 2018

BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration.
Proceedings of the Runtime Verification - 18th International Conference, 2018

Sparsity in Deep Neural Networks - An Empirical Investigation with TensorQuant.
Proceedings of the ECML PKDD 2018 Workshops, 2018

Efficient coding scheme for DDR4 memory subsystems.
Proceedings of the International Symposium on Memory Systems, 2018

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving.
Proceedings of the International Symposium on Memory Systems, 2018

25 Years of Turbo Codes: From Mb/s to beyond 100 Gb/s.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

When Channel Coding Hits the Implementation Wall.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A Low-Complexity Projection Algorithm for ADMM-Based LP Decoding.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

The Role of Memories in Transprecision Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Reconfigurable Accelerator for Morphological Operations.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Improved Maximum-Likelihood Decoding Using Sparse Parity-Check Matrices.
Proceedings of the 25th International Conference on Telecommunications, 2018

FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization.
Proceedings of the ACM Symposium on Document Engineering 2018, 2018

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

The transprecision computing paradigm: Concept, design, and applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the error behavior of DRAM by exploiting its Z-channel property.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.
Signal Processing Systems, 2017

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.
International Journal of Parallel Programming, 2017

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.
International Journal of Parallel Programming, 2017

A Platform to Analyze DDR3 DRAM's Power and Retention Time.
IEEE Design & Test, 2017

The memory challenge in computing systems: A survey.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Advanced wireless digital baseband signal processing beyond 100 Gbit/s.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Real-Time Financial Risk Measurement of Dynamic Complex Portfolios with Python and PyOpenCL.
Proceedings of the 7th Workshop on Python for High-Performance and Scientific Computing, 2017

TensorQuant: A Simulation Toolbox for Deep Neural Network Quantization.
Proceedings of the Machine Learning on HPC Environments, 2017

System simulation with gem5 and SystemC: The keystone for full interoperability.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Supervised testing of concurrent software in embedded systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A new state model for DRAMs using Petri Nets.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A Bank-Wise DRAM Power Model for System Simulations.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Using run-time reverse-engineering to optimize DRAM refresh.
Proceedings of the International Symposium on Memory Systems, 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.
Proceedings of the International Symposium on Memory Systems, 2017

Near Real-Time Risk Simulation of Complex Portfolios on Heterogeneous Computing Systems with OpenCL.
Proceedings of the 5th International Workshop on OpenCL, 2017

Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Enhanced decoding for high-rate LTE Turbo-Codes with short block lengths.
Proceedings of the 2017 IEEE International Conference on Communications Workshops, 2017

An advanced embedded architecture for connected component analysis in industrial applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017


Bit-level pipelining for highly parallel turbo-code decoders: A critical assessment.
Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2016
Increasing sampling efficiency for the fixed degree sequence model with phase transitions.
Social Netw. Analys. Mining, 2016

A cross layer approach for efficient thermal management in 3D stacked SoCs.
Microelectron. Reliab., 2016

Precision-tuning and hybrid pricer for closed-form solution-based Heston calibration.
Concurrency and Computation: Practice and Experience, 2016

A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256).
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016

Exploring system performance using elastic traces: Fast, accurate and portable.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A new bank sensitive DRAMPower model for efficient design space exploration.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Reverse Engineering of DRAMs: Row Hammer with Crosshair.
Proceedings of the Second International Symposium on Memory Systems, 2016

ConGen: An Application Specific DRAM Memory Controller Generator.
Proceedings of the Second International Symposium on Memory Systems, 2016

On the applicability of trellis compression to Turbo-Code decoder hardware architectures.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Advanced iterative channel coding schemes: When Shannon meets Moore.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

ADMM versus simplex algorithm for LP decoding.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

IMU-based determination of fatigue during long sprint.
Proceedings of the 2016 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2016

Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Error resilience and energy efficiency: An LDPC decoder design study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient reliability management in SoCs - an approximate DRAM perspective.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Application-aware cross-layer reliability analysis and optimization.
it - Information Technology, 2015

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework.
IPSJ Trans. System LSI Design Methodology, 2015

Optimization strategies for portable code for Monte Carlo-based value-at-risk systems.
Proceedings of the 8th Workshop on High Performance Computational Finance, 2015

A high-level DRAM timing, power and area exploration tool.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Latency reduction for LTE/LTE-A turbo-code decoders by on-the-fly calculation of CRC.
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

A new architecture for high throughput, low latency NB-LDPC check node processing.
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Custom Computing System for Finding Similarties in Complex Networks.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Syndrome based check node processing of high order NB-LDPC decoders.
Proceedings of the 22nd International Conference on Telecommunications, 2015

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting Phase Transitions for the Efficient Sampling of the Fixed Degree Sequence Model.
Proceedings of the 2015 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining, 2015

2014
A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers.
ACM Trans. Embedded Comput. Syst., 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014

Reliability analysis of MIMO channel preprocessing by fault injection.
Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014

Optimized active and power-down mode refresh control in 3D-DRAMs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A systematic methodology for analyzing closed-form Heston pricer regarding their accuracy and runtime.
Proceedings of the 7th Workshop on High Performance Computational Finance, 2014

A simplex algorithm for LP decoding hardware.
Proceedings of the 25th IEEE Annual International Symposium on Personal, 2014

Advanced hardware architecture for soft decoding Reed-Solomon codes.
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

A Wearable Inertial Sensor Unit for Jump Diagnosis in Multiple Athletes.
Proceedings of the 2nd International Congress on Sports Sciences Research and Technology Support, 2014

Monitoring household activities and user location with a cheap, unobtrusive thermal sensor array.
Proceedings of the 2014 ACM Conference on Ubiquitous Computing, UbiComp '14, Seattle, WA, 2014

HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Hardware implementation of a Reed-Solomon soft decoder based on information set decoding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Technology transfer towards Horizon 2020.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Feedforward carrier synchronization for pilotless bursts of DVB-RCS2.
Proceedings of the 9th International Symposium on Communication Systems, 2014

Mixed precision multilevel Monte Carlo on hybrid computing systems.
Proceedings of the IEEE Conference on Computational Intelligence for Financial Engineering & Economics, 2014

2013
Exploration and Optimization of 3-D Integrated DRAM Subsystems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Performance evaluation of ambient services by combining robotic frameworks and a smart environment platform.
Robotics Auton. Syst., 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro, 2013

Cross-Layer Error Resilience and Its Application to Wireless Communication Systems.
J. Low Power Electronics, 2013

A new dimension of parallelism in ultra high throughput LDPC decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Loopy - An open-source TCP/IP rapid prototyping and validation framework.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration.
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013

Activity recognition and nutrition monitoring in every day situations with a textile capacitive neckband.
Proceedings of the 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2013

A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model.
Proceedings of the Design, Automation and Test in Europe, 2013

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Code-aided synchronization with QPSK, 8-PSK and 16-QAM modulations.
Proceedings of the 19th Asia-Pacific Conference on Communications, 2013

2012
Design Space of Flexible Multigigabit LDPC Decoders.
VLSI Design, 2012

A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision.
Int. J. Reconfig. Comp., 2012

Reliability study on system memories of an iterative MIMO-BICM system.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

FPGA-based rapid prototyping platform for MIMO-BICM design space exploration.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A 2.15GBit/s turbo code decoder for LTE advanced base station applications.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

Combining robotic frameworks with a smart environment framework: MCA2/SimVis3D and TinySEP.
Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012

Dependable embedded systems: The German research foundation DFG priority program SPP 1500.
Proceedings of the 17th IEEE European Test Symposium, 2012

A Parallel Adaptive Range Coding Compressor: Algorithm, FPGA Prototype, Evaluation.
Proceedings of the 2012 Data Compression Conference, Snowbird, UT, USA, April 10-12, 2012, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DRAM selection and configuration for real-time mobile systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Case Study on Error Resilient Architectures for Wireless Communication.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
On Complexity, Energy- and Implementation-Efficiency of Channel Decoders.
IEEE Trans. Communications, 2011

A monolithic LTE interleaver generator for highly parallel SMAP decoders.
Proceedings of the 2011 Wireless Telecommunications Symposium, 2011

Algorithmic complexity in the heston model: an implementation view.
Proceedings of the WHPCF'11, 2011

Validation of channel decoding ASIPs a case study.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Energy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing.
Proceedings of the Knowledge-Based and Intelligent Information and Engineering Systems, 2011

A scalable multi-ASIP architecture for standard compliant trellis decoding.
Proceedings of the International SoC Design Conference, 2011

Bringing C++ productivity to VHDL world: From language definition to a case study.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Design space exploration for 3D-stacked DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2011


Reliability: A Cross-Disciplinary and Cross-Layer Approach.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
A separation algorithm for improved LP-decoding of linear block codes.
IEEE Trans. Information Theory, 2010

Implementation comparisons of the QR decomposition for MIMO detection.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform Distributions.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Low-complexity iteration control for MIMO-BICM systems.
Proceedings of the IEEE 21st International Symposium on Personal, 2010

AmICA - A Flexible, Compact, Easy-to-Program and Low-Power WSN Platform.
Proceedings of the Mobile and Ubiquitous Systems: Computing, Networking, and Services, 2010

A 477mW NoC-based digital baseband for MIMO 4G SDR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Fully integrated UWB impulse transmitter and 402-to-405MHz super-regenerative receiver for medical implant devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Complete Verification of Weakly Programmable IPs against Their Operational ISA Model.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

A 150Mbit/s 3GPP LTE Turbo code decoder.
Proceedings of the Design, Automation and Test in Europe, 2010

FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
Energy simulation of embedded XScale systems with XEEMU.
J. Embedded Computing, 2009

DRAM power management and energy consumption: a critical assessment.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Valid inequalities for binary linear codes.
Proceedings of the IEEE International Symposium on Information Theory, 2009

A novel LDPC decoder for DVB-S2 IP.
Proceedings of the Design, Automation and Test in Europe, 2009

Error correction in single-hop wireless sensor networks - A case study.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment.
IEEE Trans. VLSI Syst., 2008

Designing efficient irregular networks for heterogeneous systems-on-chip.
J. Syst. Archit., 2008

Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Fully integrated self-quenched super-regenerative UWB impulse detector.
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-specific reconfigurable processors.
Proceedings of the FPL 2008, 2008

A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment.
Proceedings of the Design, Automation and Test in Europe, 2008

A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder.
Proceedings of the Design, Automation and Test in Europe, 2008


2007
A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A Reliability-Aware LDPC Code Decoding Algorithm.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Implementation Issues of Turbo Synchronization with Duo-Binary Turbo Decoding.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

XEEMU: An Improved XScale Power Simulator.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Evaluation of High Throughput Turbo-Decoder Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low complexity LDPC code decoders for next generation standards.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Fast convergence algorithm for LDPC Codes.
Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding.
Proceedings of the IEEE 17th International Symposium on Personal, 2006

Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Disclosing the LDPC code decoder design space.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Reconfigurable Outer Modem Platform for Future Communications Systems.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005
A Scalable System Architecture for High-Throughput Turbo-Decoders.
VLSI Signal Processing, 2005

Architecture-driven voltage scaling for high-throughput turbo-decoders.
J. Embedded Computing, 2005

Network-on-chip-centric approach to interleaving in high throughput channel decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energieminimierung von Basisbandsignalverarbeitungsalgorithmen auf programmierbaren Plattformen.
Proceedings of the INFORMATIK 2005, 2005

A Synthesizable IP Core for DVB-S2 LDPC Code Decoding.
Proceedings of the 2005 Design, 2005

Power Optimization in advanced Channel Coding.
Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

2004
A multi-standard channel-decoder for base-station applications.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

FPGA implementation of parallel turbo-decoders.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.
Proceedings of the Integrated Circuit and System Design, 2004

Joint graph-decoder design of IRA codes on scalable architectures [LDPC codes].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Channel Decoder Architecture for 3G Mobile Wireless Terminals.
Proceedings of the 2004 Design, 2004

Design methodology for IRA codes.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Vergleich von Hardware- und Software-Implementierungen in der digitalen Kommunikation am Beispiel der Kanalcodierung (Hardware-/Software Trade-Offs in Digital Communication Systems with Special Emphasis on Channel-Coding).
it - Information Technology, 2003

System-on-Chip - Ein Sonderheft anlässlich des 60. Geburtstages von Prof. Dr. Dr. h.c. mult. Manfred Glesner.
it - Information Technology, 2003

Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders.
Proceedings of the Integrated Circuit and System Design, 2003

Concurrent interleaving architectures for high-throughput channel coding.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

VLSI-implementation issues of turbo trellis-coded modulation.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .
Proceedings of the 2003 Design, 2003

2002
Enabling high-speed turbo-decoding through concurrent interleaving.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Evaluation of algorithm optimizations for low-power Turbo-Decoder implementations.
Proceedings of the IEEE International Conference on Acoustics, 2002

Hardware/Software Trade-Offs for Advanced 3G Channel Coding.
Proceedings of the 2002 Design, 2002

2001
Turbo-decoder quantization for UMTS.
IEEE Communications Letters, 2001

Embedded DRAM Development: Technology, Physical Design, and Application Issues.
IEEE Design & Test of Computers, 2001

Vlsi Architectures For High-Speed Map Decoders.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Embedded Memories in System Design: Technology, Application, Design and Tools.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design of low-power high-speed maximum a priori decoder architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Low power implementation of a turbo-decoder on programmable architectures.
Proceedings of ASP-DAC 2001, 2001

2000
Turbo-decoding without SNR estimation.
IEEE Communications Letters, 2000

Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths.
Proceedings of the 2000 Design, 2000

1998
Issues in Embedded DRAM Development and Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Embedded DRAM Architectural Trade-Offs.
Proceedings of the 1998 Design, 1998

1997
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.
ACM Trans. Design Autom. Electr. Syst., 1997

1995
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers, 1994

Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Scheduling of behavioral VHDL by retiming techniques.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
The Siemens high-level synthesis system CALLAS.
IEEE Trans. VLSI Syst., 1993

Estimating lower hardware bounds in high-level synthesis.
Proceedings of the VLSI 93, 1993

Synthesis of complex VHDL operators.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Data Part Optimizations in the CALLAS Synthesis Environment.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

High-level synthesis in a rapid-prototype environment for mechatronic systems.
Proceedings of the conference on European design automation, 1992

1991
A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment.
Proceedings of the VLSI 91, 1991

A VLSI System Design for the Control of High Performance Combustion Engines.
Proceedings of the VLSI 91, 1991

RAMSES-a rapid prototyping environment for embedded control applications.
Proceedings of the Second International Workshop on Rapid System Prototyping, 1991

A new approach to timing driven partitioning of combinational logic.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

HADES-high-level architecture development and exploration system.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

1990
Timing Driven Partitioning of Combinational Logic.
Proceedings of the Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990

1989
Effiziente Verfahren für den physikalischen Entwurf von MOS-VLSI-Schaltungen und ihre Anwendung beim Entwurf eines defekttoleranten Mikroprozessors.
PhD thesis, 1989

1988
A Defect-Tolerant and Fully Testable PLA.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Statische und dynamische CMOS-Schaltungstechniken im Vergleich.
it - Informationstechnik, 1986


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