Christian Weis

Carl Christian Rheinländer

Deepak M. Mathew

IEEE Des. Test, 2017

A Bank-Wise DRAM Power Model for System Simulations.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Using run-time reverse-engineering to optimize DRAM refresh.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

An advanced embedded architecture for connected component analysis in industrial applications.

[BibT_eX]

[DOI]

Menbere Tekleyohannes

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

A cross layer approach for efficient thermal management in 3D stacked SoCs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

A new bank sensitive DRAMPower model for efficient design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Reverse Engineering of DRAMs: Row Hammer with Crosshair.

[BibT_eX]

[DOI]

Carl Christian Rheinländer

Daniel Müller-Gritschneder

Proceedings of the Second International Symposium on Memory Systems, 2016

ConGen: An Application Specific DRAM Memory Controller Generator.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

Error resilience and energy efficiency: An LDPC decoder design study.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient reliability management in SoCs - an approximate DRAM perspective.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Application-aware cross-layer reliability analysis and optimization.

[BibT_eX]

[DOI]

Fabian Oboril

Ulf Schlichtmann

Mehdi Baradaran Tahoori

Jürgen Teich

it Inf. Technol., 2015

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

A high-level DRAM timing, power and area exploration tool.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Custom Computing System for Finding Similarties in Complex Networks.

[BibT_eX]

[DOI]

Christian de Schryver

Katharina Anna Zweig

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Optimized active and power-down mode refresh control in 3D-DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting expendable process-margins in DRAMs for run-time performance optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Exploration and Optimization of 3-D Integrated DRAM Subsystems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.

[BibT_eX]

[DOI]

Veit Kleeberger

Christina Gimmler-Dumont

Daniel Mueller-Gritschneder

Andreas Herkersdorf

Sani R. Nassif

Ulf Schlichtmann

IEEE Micro, 2013

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ.

[BibT_eX]

[DOI]

Proceedings of the 10th FPGAworld Conference, 2013

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Towards variation-aware system-level power estimation of DRAMs: an empirical approach.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Design Space of Flexible Multigigabit LDPC Decoders.

[BibT_eX]

[DOI]

VLSI Design, 2012

A 2.15GBit/s turbo code decoder for LTE advanced base station applications.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm.

[BibT_eX]

[DOI]

Ivan Shcherbakov

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing, Networking and Communications, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DRAM selection and configuration for real-time mobile systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Bringing C++ productivity to VHDL world: From language definition to a case study.

[BibT_eX]

[DOI]

Ivan Shcherbakov