Mónico Linares Aranda

Orcid: 0000-0001-6206-0816

According to our database1, Mónico Linares Aranda authored at least 32 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Hourglass and Semi-Hourglass layout techniques to improve radiation hardening of NMOS devices.
Proceedings of the 20th International Conference on Electrical Engineering, 2023

2021
Degradation performance analysis and operation optimization of rotary-traveling wave oscillators for RF-CMOS applications.
Microelectron. J., 2021

Analysis of On-Silicon-Vias for an Advanced RF-CMOS Process: Experimental Characterization and Modeling.
Proceedings of the 18th International Conference on Electrical Engineering, 2021

2020
Characterization and modeling of on-chip via stacks for RF-CMOS applications.
IEICE Electron. Express, 2020

Impact and Modeling of Möbius Connection in the Rotary Traveling Wave Oscillator Performance.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
Electromagnetic analysis of via arrays for different RF-CMOS technological nodes.
Proceedings of the 16th International Conference on Electrical Engineering, 2019

2018
Semiempirical Model for IC Interconnects Considering the Coupling Between the Signal Trace and the Ground Plane.
Circuits Syst. Signal Process., 2018

An analysis of on-silicon-via stacks in RF-CMOS processes.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
A simple model of inter-metallic connections (vias) in CMOS resonant rotary traveling wave oscillator (RTWO).
Proceedings of the 14th International Conference on Electrical Engineering, 2017

Topology and discontinuities effect on CMOS rotary traveling wave oscillators.
Proceedings of the 14th International Conference on Electrical Engineering, 2017

Anisotropic silicon etch to house CMOS compatible MEMS microstructures without planarization techniques.
Proceedings of the 14th International Conference on Electrical Engineering, 2017

2016
Test structures for residual stress monitoring in the integrated CMOS-MEMS process development.
Proceedings of the 13th International Conference on Synthesis, 2016

A set of test structures for the development of a CMOS-MEMS technology.
Proceedings of the 13th International Conference on Electrical Engineering, 2016

2014
Study of on-chip vias of resonant rotary traveling wave oscillators.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Analysis of the impact of vias on resonant rotary traveling wave oscillators.
Proceedings of the 11th International Conference on Electrical Engineering, 2014

2013
Effect of changing the material and device's properties on the performance of polysilicon-based MicroActuators.
Proceedings of the 10th International Conference on Electrical Engineering, 2013

2011
CMOS Full-Adders for Energy-Efficient Arithmetic Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2011

New High-Performance Full Adders Using an Alternative Logic Structure.
Computación y Sistemas, 2011

An experimental comparison of expanded voltage controlled oscillators for system's synchronization.
Proceedings of the 8th International Conference on Electrical Engineering, 2011

2010
Hybrid adders for high-speed arithmetic circuits: A comparison.
Proceedings of the 7th International Conference on Electrical Engineering, 2010

Transmission line characterization for high frequency synchronization systems design.
Proceedings of the 20th International Conference on Electronics, 2010

2008
On-chip clock network using interconnected and coupled ring oscillators.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Design of 2 Stages Ring Oscillators Applying Local Networks of Feedback.
Proceedings of the 18th International Conference on Electronics, 2008

2005
An alternative logic approach to implement high-speed low-power full adder cells.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

2004
The noise immunity of dynamic digital circuits with technology scaling.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An improved technique to increase noise-tolerance in dynamic digital circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An architecture for fractal image compression using quad-tree multiresolution.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low power and high speed CMOS Voltage-Controlled Ring Oscillator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analysis and verification of interconnected rings as clock distribution networks.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Interconnected rings and oscillators as gigahertz clock distribution nets.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
A new technique for noise-tolerant pipelined dynamic digital circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Analysis of clock distribution networks in the presence of crosstalk and groundbounce.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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