Víctor H. Champac

According to our database1, Víctor H. Champac authored at least 78 papers between 1991 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2019
Modeling and Detectability of Full Open Gate Defects in FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects.
J. Electron. Test., 2019

Identification of Logic Paths Influenced by Severe Coupling Capacitances.
Proceedings of the IEEE Latin American Test Symposium, 2019

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells.
Proceedings of the IEEE Latin American Test Symposium, 2019

B-open: A New Defect in Nanometer Technologies due to SADP Process.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects.
ACM Trans. Design Autom. Electr. Syst., 2018

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells.
J. Electron. Test., 2018

An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

A metric-guided gate-sizing methodology for aging guardband reduction.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
Analysis of short defects in FinFET based logic cells.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
Microelectron. Reliab., 2016

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage.
J. Low Power Electron., 2016

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability.
J. Electron. Test., 2016

A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage.
Proceedings of the 17th Latin-American Test Symposium, 2016

Critical path selection under NBTI/PBTI aging for adaptive frequency tuning.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Behavior and test of open-gate defects in FinFET based cells.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Screening small-delay defects using inter-path correlation to reduce reliability risk.
Microelectron. Reliab., 2015

Low V<sub>DD</sub> and body bias conditions for testing bridge defects in the presence of process variations.
Microelectron. J., 2015

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Circuit performance optimization for local intra-die process variations using a gate selection metric.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell.
Proceedings of the 16th Latin-American Test Symposium, 2015

Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability.
Proceedings of the 16th Latin-American Test Symposium, 2015

Message from the LATS2015 Chairs.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
Skew violation verification in digital interconnect signals based on signal addition.
IEICE Electron. Express, 2014

Hot topic session 12B: Stay relevant with standards-based DFT.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Analysis of fin height on FinFET SRAM cell hardening.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies.
Proceedings of the 15th Latin American Test Workshop, 2014

2013
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion.
J. Electron. Test., 2013

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths.
IEEE Des. Test, 2013

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias.
Proceedings of the 14th Latin American Test Workshop, 2013

2012
Resistive bridge defect detection enhancement under parameter variations combining Low V<sub>DD</sub> and body bias in a delay based test.
Microelectron. Reliab., 2012

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.
IEEE Des. Test Comput., 2012

Testing of Stuck-Open Faults in Nanometer Technologies.
IEEE Des. Test Comput., 2012

Small-delay defects detection under process variation using Inter-Path Correlation.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low voltage testing for interconnect opens under process variations.
Proceedings of the 13th Latin American Test Workshop, 2012

2011
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.
J. Low Power Electron., 2011

Computing the Detection Probability for Small Delay Defects of Nanometer ICs.
J. Electron. Test., 2011

A new methodology for realistic open defect detection probability evaluation under process variations.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Low-sensitivity to process variations aging sensor for automotive safety-critical applications.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Predictive error detection by on-line aging monitoring.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs.
Proceedings of the 15th European Test Symposium, 2010

Programmable aging sensor for automotive safety-critical applications.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Stuck-Open Fault Leakage and Testing in Nanometer Technologies.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Built-in aging monitoring for safety-critical applications.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Detectability analysis of small delays due to resistive opens considering process variations.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.
J. Electron. Test., 2008

Testing Skew and Logic Faults in SoC Interconnects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A design methodology for logic paths tolerant to local intra-die variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2005
Testing of resistive opens in CMOS latches and flip-flops.
Proceedings of the 10th European Test Symposium, 2005

Test of Interconnection Opens Considering Coupling Signals.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Guest Editorial.
J. Electron. Test., 2004

The noise immunity of dynamic digital circuits with technology scaling.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An improved technique to increase noise-tolerance in dynamic digital circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Signal integrity verification using high speed monitors.
Proceedings of the 9th European Test Symposium, 2004

Analysis and Attenuation Proposal in Ground Bounce.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Guest Editorial.
J. Electron. Test., 2003

Signal integrity loss in bus lines due to open shielding defects.
Proceedings of the 8th European Test Workshop, 2003

2002
A new technique for noise-tolerant pipelined dynamic digital circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Detectability Conditions of Full Opens in the Interconnections.
J. Electron. Test., 2001

Guest Editorial.
J. Electron. Test., 2001

Resistive Opens in a Class of CMOS Latches: Analysis and DFT.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000
CGTDEMO - educational software for the central limit theorem.
ACM SIGCSE Bull., 2000

Detectability Conditions for Interconnection Open Defect.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999
IDDQ Testing of Opens in CMOS SRAMs.
J. Electron. Test., 1999

1995
Testability of floating gate defects in sequential circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994
Electrical model of the floating gate defect in CMOS ICs: implications on I<sub>DDQ</sub> testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993
Analysis of the Floating Gate Defect in CMOS.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
Quiescent current analysis and experimentation of defective CMOS circuits.
J. Electron. Test., 1992

1991
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991


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