Morteza Gholipour

Orcid: 0000-0001-6290-9461

According to our database1, Morteza Gholipour authored at least 25 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM.
Microelectron. J., 2022

Improved read/write assist mechanism for 10-transistor static random access memory cell.
Int. J. Circuit Theory Appl., 2022

A low-leakage single-bitline 9T SRAM cell with read-disturbance removal and high writability for low-power biomedical applications.
Int. J. Circuit Theory Appl., 2022

Enhanced overloaded code division multiple access for network on chip.
IET Comput. Digit. Tech., 2022

A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology.
Circuits Syst. Signal Process., 2022

Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications.
Circuits Syst. Signal Process., 2022

Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology.
Microelectron. J., 2021

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design.
Int. J. Circuit Theory Appl., 2021

Single-ended half-select disturb-free 11T static random access memory cell for reliable and low power applications.
Int. J. Circuit Theory Appl., 2021

Design space exploration of low-power flip-flops in FinFET technology.
Integr., 2020

Nanoscale field effect diode (FED) with improved speed and <i>I</i> <sub>ON</sub>/<i>I</i> <sub>OFF</sub> ratio.
IET Circuits Devices Syst., 2019

Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations.
Microelectron. J., 2014

Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures.
Microelectron. J., 2013

Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Graphene nano-ribbon field-effect transistors as future low-power devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Efficient inclusive analytical model for delay estimation of multi-walled carbon nanotube interconnects.
IET Circuits Devices Syst., 2012

A comparative study of nanowire crossbar and MOSFET logic implementations.
Proceedings of EUROCON 2011, 2011

Design and Implementation of Lifting Based Integer Wavelet Transform for Image Compression Applications.
Proceedings of the Digital Information and Communication Technology and Its Applications, 2011

Comparative study of asynchronous pipeline design methods.
IEICE Electron. Express, 2006

An efficient model for performance analysis of asynchronous pipeline design methods.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005