Ali Afzali-Kusha
Orcid: 0000-0001-8614-2007
According to our database1,
Ali Afzali-Kusha
authored at least 189 papers
between 2001 and 2023.
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Bibliography
2023
A<sup>2</sup>P-MANN: Adaptive Attention Inference Hops Pruned Memory-Augmented Neural Networks.
IEEE Trans. Neural Networks Learn. Syst., November, 2023
ACM Trans. Design Autom. Electr. Syst., July, 2023
Federated learning by employing knowledge distillation on edge devices with limited hardware resources.
Neurocomputing, April, 2023
ACM Trans. Design Autom. Electr. Syst., January, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Neurocomputing, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
OPTIMA: An Approach for Online Management of Cache Approximation Levels in Approximate Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level.
ACM Trans. Design Autom. Electr. Syst., 2021
LATIM: Loading-Aware Offline Training Method for Inverter-Based Memristive Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Reliability Enhancement of Inverter-Based Memristor Crossbar Neural Networks Using Mathematical Analysis of Circuit Non-Idealities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
CoRR, 2021
CoRR, 2021
2020
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Offline Training Improvement of Inverter-Based Memristive Neural Networks Using Inverter Voltage Characteristic Smoothing.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx.
Proc. IEEE, 2020
2019
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Low-power data encoding/decoding for energy-efficient static random access memory design.
IET Circuits Devices Syst., 2019
CoRR, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Micro, 2018
An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.
IEEE Internet Things J., 2018
Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.
Integr., 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit.
Integr., 2017
CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode.
Integr., 2017
Comput. Electr. Eng., 2017
An energy and area efficient yet high-speed square-root carry select adder structure.
Comput. Electr. Eng., 2017
TruncApp: A truncation-based approximate divider for energy efficient DSP applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions.
ACM Trans. Design Autom. Electr. Syst., 2016
All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs.
Microelectron. Reliab., 2016
An efficient temperature dependent hot carrier injection reliability simulation flow.
Microelectron. Reliab., 2016
Integr., 2016
Power and energy reduction of racetrack-based caches by exploiting shared shift operations.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2015
OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs.
ACM Trans. Embed. Comput. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits.
Microelectron. Reliab., 2015
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015
A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages.
Int. J. Circuit Theory Appl., 2015
Simultaneous power control and power management algorithm with sector-shaped topology for wireless sensor networks.
EURASIP J. Wirel. Commun. Netw., 2015
An efficient network on-chip architecture based on isolating local and non-local communications.
Comput. Electr. Eng., 2015
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
A heuristic machine learning-based algorithm for power and thermal management of heterogeneous MPSoCs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. Reliab., 2014
Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014
Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors.
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Delay variation analysis in the presence of power supply noise in nano-scale digital VLSI circuits.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Improving efficiency of extensible processors by using approximate custom instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities.
Microelectron. Reliab., 2013
Microprocess. Microsystems, 2013
A new merit function for custom instruction selection under an area budget constraint.
Des. Autom. Embed. Syst., 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Capturing and mitigating the NBTI effect during the design flow for extensible processors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
2012
Probability calculation of read failures in nano-scaled SRAM cells under process variations.
Microelectron. Reliab., 2012
Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability.
Microelectron. Reliab., 2012
High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility.
J. Zhejiang Univ. Sci. C, 2012
An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling.
J. Zhejiang Univ. Sci. C, 2012
J. Low Power Electron., 2012
Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution.
IET Circuits Devices Syst., 2012
EURASIP J. Wirel. Commun. Netw., 2012
HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture.
Comput. Electr. Eng., 2012
Proceedings of the 1st Mediterranean Conference on Embedded Computing, 2012
An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
An architecture-level approach for mitigating the impact of process variations on extensible processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement.
Microelectron. Reliab., 2011
Compact modeling of short-channel effects in symmetric and asymmetric 3-T/4-T double gate MOSFETs.
Microelectron. Reliab., 2011
IEICE Electron. Express, 2011
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects.
Microelectron. Reliab., 2010
A low-power and low-energy flexible GF(<i>p</i>) elliptic-curve cryptography processor.
J. Zhejiang Univ. Sci. C, 2010
J. Syst. Archit., 2010
IEICE Electron. Express, 2010
ATC - An Asymmetric Topology Control Algorithm for Heterogeneous Wireless Sensor Networks.
Proceedings of the WINSYS 2010 - Proceedings of the International Conference on Wireless Information Networks and Systems, Athens, Greece, July 26, 2010
Statistical delay modeling of read operation of SRAMs due to channel length variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
J. Signal Process. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips.
J. Low Power Electron., 2009
A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution.
J. Low Power Electron., 2009
IET Comput. Digit. Tech., 2009
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Very Low-power Flexible GF(p) Elliptic-curve Crypto-processor for Non-time-critical Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
IEICE Electron. Express, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEICE Electron. Express, 2007
IEICE Electron. Express, 2007
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proc. IEEE, 2006
J. Low Power Electron., 2006
IEICE Electron. Express, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Optimization of the V<sub>T</sub> control method for low-power ultra-thin double-gate SOI logic circuits.
Integr., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Enhancing the efficiency of cluster voltage scaling technique for low-power application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 Design, 2005
2004
Accurate and efficient modeling of SOI MOSFET with technology independent neural networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Mixed RL-Huffman encoding for power reduction and data compression in scan test.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Event-driven dynamic power management based on wavelet forecasting theory.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
2003
Proceedings of the Integrated Circuit and System Design, 2003
A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Fast center-line extraction for quantification of vessels in confocal microscopy images.
Proceedings of the 2002 IEEE International Symposium on Biomedical Imaging, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001