Moslem Didehban

Orcid: 0000-0002-9357-4702

According to our database1, Moslem Didehban authored at least 13 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication.
IEEE Trans. Dependable Secur. Comput., 2024

2022
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults.
ACM Trans. Archit. Code Optim., 2022

2021
CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Software Approaches for In-time Resilience.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Software Techniques For Dependable Execution.
PhD thesis, 2018

A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments.
IEEE Trans. Reliab., 2018

EXPERT: Effective and flexible error protection by redundant multithreading.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
NEMESIS: A software approach for computing in presence of soft errors.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

InCheck: An In-application Recovery Scheme for Soft Errors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
nZDC: a compiler technique for near zero silent data corruption.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2011
A Gate Level Analysis of Transient Faults Effects on Dual-Core Chip-Multi Processors.
Proceedings of the Sixth International Conference on Availability, 2011

2010
Analysis of Transient Faults on a MIPS-Based Dual-Core Processor.
Proceedings of the ARES 2010, 2010


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