Mostafa M. Ayesh
Orcid: 0000-0002-3814-2288
According to our database1,
Mostafa M. Ayesh
authored at least 9 papers
between 2015 and 2025.
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Bibliography
2025
11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter.
IEEE J. Solid State Circuits, December, 2024
5.3 A 0.072mm<sup>2</sup> 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2016
Design and analysis of a low-power high-speed charge-steering based StrongARM comparator.
Proceedings of the 28th International Conference on Microelectronics, 2016
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015