Moxiao Lou
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Bibliography
2025
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025
A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025