Humiao Li
Orcid: 0009-0009-3508-982X
According to our database1,
Humiao Li authored at least 5 papers
between 2024 and 2026.
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Bibliography
2026
7.8 A 55nm Intelligent Vision SoC Achieving 346TOPS/W System Efficiency via Fully Analog Sensing-to-Inference Pipeline.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 40-nm Resilient MLC RRAM Macro with Self-Referenced Time-Based Readout and 3-Bit Interleaved ECC Achieving 0.22 pJ/bit Read Energy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025
A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 0.72nW, 0.006mm<sup>2</sup> 32kHz Crystal Oscillator with Adaptive Sub-Harmonic Pulse Injection from -40°C to 125°C in 22nm FDSOI.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024