Zhengke Yang

According to our database, Zhengke Yang authored at least 10 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

VeRA+: Vector-Based Lightweight Digital Compensation for Drift-Resilient RRAM In-Memory Computing.

Weirong Dong, Kai Zhou, Zhen Kong, Zhengke Yang, Quan Cheng, Haoyuan Li, Junkai Huang, Jun Lan, Yida Li, Masanori Hashimoto, Longyang Lin

CoRR, March, 2026

7.8 A 55nm Intelligent Vision SoC Achieving 346TOPS/W System Efficiency via Fully Analog Sensing-to-Inference Pipeline.

Zhengke Yang, Haofeng Yu, Xiao Liu, Zhen Kong, Humiao Li, Liang Ran, Zhichao Lyu, Xinhe Feng, Liang Zhao, Yida Li, Jiamin Li, Feichi Zhou, Longyang Lin

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications.

Quan Cheng, Zhengke Yang, Haoyuan Li, Qiufeng Li, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jerald Yoo, Masanori Hashimoto, Longyang Lin

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS.

Moxiao Lou, Jin Wang, Humiao Li, Zhengke Yang, Quan Cheng, Jiamin Li, Masanori Hashimoto, Longyang Lin

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

Efficient Calibration for RRAM-based In-Memory Computing using DoRA.

Weirong Dong, Kai Zhou, Zhen Kong, Quan Cheng, Junkai Huang, Zhengke Yang, Masanori Hashimoto, Longyang Lin

CoRR, April, 2025

A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers.

Jin Wang, Moxiao Lou, Zhengke Yang, Ruijie Peng, Humiao Li, Weirong Dong, Haoran Lyu, Yida Li, Jiamin Li, Hao Yu, Jerald Yoo, Longyang Lin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping.

Quan Cheng, Longyang Lin, Mingqiang Huang, Qiufeng Li, Zhengke Yang, Liuyao Dai, Hao Yu, Yu-Jen Chen, Yiyu Shi, Masanori Hashimoto

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2022

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.

Kai Li, Wei Mao, Junzhuo Zhou, Boyu Li, Zhengke Yang, Shuxing Yang, Laimin Du, Sixiao Huang, Hao Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.

Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.

Kai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022