Masanori Hashimoto
Orcid: 0000-0002-0377-2108Affiliations:
- Kyoto University, Sakyo, Japan
- Osaka University, Suita, Japan
- Kyoto University, Sakyo, Japan (PhD 2001)
According to our database1,
Masanori Hashimoto
authored at least 220 papers
between 1998 and 2023.
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Bibliography
2023
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA.
Integr., March, 2023
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers.
Proceedings of the Companion Proceedings of the 28th International Conference on Intelligent User Interfaces, 2023
Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Performance comparison of memristor crossbar-based analog and FPGA-based digital weight-memory-less neural networks.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE J. Solid State Circuits, 2022
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter.
IEICE Trans. Inf. Syst., 2022
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs.
Proceedings of the IUI 2022: 27th International Conference on Intelligent User Interfaces, Helsinki, Finland, March 22 - 25, 2022, 2022
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Access, 2021
Proceedings of the SIGGRAPH Asia 2021 Posters, Tokyo, Japan, December 14-17, 2021., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 32nd British Machine Vision Conference 2021, 2021
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training.
Integr., 2020
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing.
Proceedings of the IEEE International Test Conference, 2020
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction.
Proceedings of the IEEE International Test Conference, 2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Integr., 2019
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate.
IEICE Trans. Electron., 2019
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes.
Proceedings of the 24th International Conference on Intelligent User Interfaces: Companion, 2019
Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019
2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol., 2018
An analytic evaluation on soft error immunity enhancement due to temporal triplication.
Int. J. Embed. Syst., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEEE Embed. Syst. Lett., 2018
Hold violation analysis for functional test of ultra-low temperature circuits at room temperature.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Comparing voltage adaptation performance between replica and in-situ timing monitors.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
Proceedings of the 55th Annual Design Automation Conference, 2018
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Integr., 2017
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017
GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction.
Proceedings of the 22nd International Conference on Intelligent User Interfaces, 2017
Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
3D node localization from node-to-node distance information using cross-entropy method.
Proceedings of the 2015 IEEE Virtual Reality, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Real-time on-chip supply voltage sensor and its application to trace-based timing error localization.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Area efficient device-parameter estimation using sensitivity-configurable ring oscillator.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
An oscillator-based true random number generator with process and temperature tolerance.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling.
IEEE Trans. Inf. Forensics Secur., 2013
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations.
Integr., 2013
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices.
IEICE Trans. Inf. Syst., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Electron. Express, 2013
PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices.
IEICE Electron. Express, 2013
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proximity distance estimation based on capacitive coupling between 1mm<sup>3</sup> sensor nodes.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Stochastic error rate estimation for adaptive speed control with field delay testing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the International SoC Design Conference, 2012
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Power gating implementation for noise mitigation with body-tied triple-well structure.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Device-parameter estimation with on-chip variation sensors considering random variability.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling.
Proceedings of the Information Security Applications - 11th International Workshop, 2010
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE J. Solid State Circuits, 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.
IEICE Trans. Electron., 2009
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
A case for exploiting complex arithmetic circuits towards performance yield enhancement.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
High performance on-chip differential signaling using passive compensation for global communication.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Inf. Syst., 2008
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Decoupling capacitance allocation for timing with statistical noise model and timing analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEICE Trans. Electron., 2007
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Trans. Electron., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Physical Design, 2003
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Experimental Study on Cell-Base High-Performance Datapath Design.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of 2002 International Symposium on Physical Design, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of ASP-DAC 2001, 2001
2000
A performance optimization method by gate sizing using statistical static timing analysis.
Proceedings of the 2000 International Symposium on Physical Design, 2000
1999
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998