Masanori Hashimoto

According to our database1, Masanori Hashimoto authored at least 192 papers between 1998 and 2020.

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Bibliography

2020
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training.
Integr., 2020

A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing.
Proceedings of the IEEE International Test Conference, 2020

Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction.
Proceedings of the IEEE International Test Conference, 2020

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Low-Cost Reservoir Computing using Cellular Automata and Random Forests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Soft Error and Its Countermeasures in Terrestrial Environment.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Memory Efficient Training using Lookup-Table-based Quantization for Neural Network.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Characterizing SRAM and FF soft error rates with measurement and simulation.
Integr., 2019

Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate.
IEICE Trans. Electron., 2019

Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes.
Proceedings of the 24th International Conference on Intelligent User Interfaces: Companion, 2019

Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Training Data Reduction using Support Vectors for Neural Networks.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019

Distilling Knowledge for Non-Neural Networks.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019

2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving.
IEEE Trans. Very Large Scale Integr. Syst., 2018

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol., 2018

An analytic evaluation on soft error immunity enhancement due to temporal triplication.
Int. J. Embed. Syst., 2018

Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
IEEE Embed. Syst. Lett., 2018

Hold violation analysis for functional test of ultra-low temperature circuits at room temperature.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Interconnect Delay Analysis for RRAM Crossbar Based FPGA.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Comparing voltage adaptation performance between replica and in-situ timing monitors.
Proceedings of the International Conference on Computer-Aided Design, 2018

Sneak path free reconfiguration of via-switch crossbars based FPGA.
Proceedings of the International Conference on Computer-Aided Design, 2018

Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
Proceedings of the 55th Annual Design Automation Conference, 2018

Hardware Architecture for Fast General Object Detection using Aggregated Channel Features.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Minimizing detection-to-boosting latency toward low-power error-resilient circuits.
Integr., 2017

Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Near-future traffic evaluation based navigation for automated driving vehicles.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017

GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction.
Proceedings of the 22nd International Conference on Intelligent User Interfaces, 2017

Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Critical path isolation for time-to-failure extension and lower voltage operation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

3D node localization from node-to-node distance information using cross-entropy method.
Proceedings of the 2015 IEEE Virtual Reality, 2015

Stochastic timing error rate estimation under process and temporal variations.
Proceedings of the 2015 IEEE International Test Conference, 2015

Soft error immune latch design for 20 nm bulk CMOS.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of package on neutron induced single event upset in 20 nm SRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Real-time on-chip supply voltage sensor and its application to trace-based timing error localization.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Area efficient device-parameter estimation using sensitivity-configurable ring oscillator.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An oscillator-based true random number generator with process and temperature tolerance.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Process and Temperature Tolerant Oscillator-Based True Random Number Generator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Opportunities and Verification Challenges of Run-Time Performance Adaptation.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Stochastic verification of run-time performance adaptation with field delay testing.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Supply Noise Suppression by Triple-Well Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling.
IEEE Trans. Inf. Forensics Secur., 2013

A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations.
Integr., 2013

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices.
IEICE Trans. Inf. Syst., 2013

Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Jitter Amplifier for Oscillator-Based True Random Number Generator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation.
IEICE Electron. Express, 2013

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices.
IEICE Electron. Express, 2013

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Proximity distance estimation based on capacitive coupling between 1mm<sup>3</sup> sensor nodes.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Stochastic error rate estimation for adaptive speed control with field delay testing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.
Proceedings of the 18th IEEE European Test Symposium, 2013

Soft error immunity of subthreshold SRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Signal-dependent analog-to-digital converter based on MINIMAX sampling.
Proceedings of the International SoC Design Conference, 2012

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Body bias clustering for low test-cost post-silicon tuning.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Extracting Device-Parameter Variations with RO-Based Sensors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Stress Probability Computation for Estimating NBTI-Induced Delay Degradation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

An oscillator-based true random number generator with jitter amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Power gating implementation for noise mitigation with body-tied triple-well structure.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Device-parameter estimation with on-chip variation sensors considering random variability.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Run-time adaptive performance compensation using on-chip sensors.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Prediction of Self-Heating in Short Intra-Block Wires.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Gate Delay Estimation in STA under Dynamic Power Supply Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Impact of Self-Heating in Wire Interconnection on Timing.
IEICE Trans. Electron., 2010

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling.
Proceedings of the Information Security Applications - 11th International Workshop, 2010

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Clock skew reduction by self-compensating manufacturing variability with on-chip sensors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform.
IEEE J. Solid State Circuits, 2009

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.
IEICE Trans. Electron., 2009

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A case for exploiting complex arithmetic circuits towards performance yield enhancement.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Coarse-grained dynamically reconfigurable architecture with flexible reliability.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

High performance on-chip differential signaling using passive compensation for global communication.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects.
IEEE J. Solid State Circuits, 2008

Area-Efficient Reconfigurable Architecture for Media Processing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Impact of Well Edge Proximity Effect on Timing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Timing Analysis Considering Temporal Supply Voltage Fluctuation.
IEICE Trans. Inf. Syst., 2008

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On-chip high performance signaling using passive compensation.
Proceedings of the 26th International Conference on Computer Design, 2008

Decoupling capacitance allocation for timing with statistical noise model and timing analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

High performance current-mode differential logic.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.
IEICE Trans. Electron., 2007

Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Proposal of Metrics for SSTA Accuracy Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Timing Analysis Considering Spatial Power/Ground Level Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Transistor Sizing of LCD Driver Circuit for Technology Migration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Future Prediction of Self-Heating in Short Intra-Block Wires.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Interconnect RL extraction at a single representative frequency.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Successive Pad Assignment for Minimizing Supply Voltage Drop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Effects of On-Chip Inductance on Power Distribution Grid.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Trans. Electron., 2005

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Statistical Analysis of Clock Skew Variation in H-Tree Structure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Interconnect capacitance extraction for system LCD circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A design scheme for sampling switch in active matrix LCD.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Design guideline for resistive termination of on-chip high-speed interconnects.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Measurement and analysis of delay variation due to inductive coupling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Return path selection for loop RL extraction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Equivalent waveform propagation for static timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Automatic Generation of Standard Cell Library in VDSM Technologies.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Performance limitation of on-chip global interconnects for high-speed signaling.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Representative frequency for interconnect R(f)L(f)C extraction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Capturing crosstalk-induced waveform for accurate static timing analysis.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Experimental Study on Cell-Base High-Performance Datapath Design.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Crosstalk noise optimization by post-layout transistor sizing.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
Increase in delay uncertainty by performance optimization.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Crosstalk Noise Estimation for Generic RC Trees.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Post-layout transistor sizing for power reduction in cell-based design.
Proceedings of ASP-DAC 2001, 2001

2000
A performance optimization method by gate sizing using statistical static timing analysis.
Proceedings of the 2000 International Symposium on Physical Design, 2000

1999
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A power optimization method considering glitch reduction by gate sizing.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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