Muhammad Adil Ansari

Orcid: 0000-0002-4675-5535

According to our database1, Muhammad Adil Ansari authored at least 10 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Highly Efficient Test Architecture for Low-Power AI Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Test Architecture for Systolic Array of Edge-Based AI Accelerator.
IEEE Access, 2021

2018
Erratum to "Time-Multiplexed-Network for Test Cost Reduction".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Time-Multiplexed 1687-Network for Test Cost Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
On Diagnosing the Aging Level of Automotive Semiconductor Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Time-multiplexed test access architecture for stacked integrated circuits.
IEICE Electron. Express, 2016

2015
Efficient diagnosis technique for aging defects on automotive semiconductor chips.
Proceedings of the 20th IEEE European Test Symposium, 2015

Scan-Puf: Puf Elements Selection Methods for Viable IC Identification.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2009
SONAR Based Obstacle Detection and Avoidance Algorithm.
Proceedings of the 2009 International Conference on Signal Acquisition and Processing, 2009


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