Sungju Park

Orcid: 0000-0003-2322-232X

According to our database1, Sungju Park authored at least 45 papers between 1990 and 2022.

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Bibliography

2022
Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Highly Efficient Test Architecture for Low-Power AI Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Time multiplexed LBIST for in-field testing of automotive AI accelerators.
IEICE Electron. Express, 2021

Master-slave based test cost reduction method for DNN accelerators.
IEICE Electron. Express, 2021

Test Architecture for Systolic Array of Edge-Based AI Accelerator.
IEEE Access, 2021

2020
CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience.
IEEE Access, 2020

2018
Erratum to "Time-Multiplexed-Network for Test Cost Reduction".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Time-Multiplexed 1687-Network for Test Cost Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
On Diagnosing the Aging Level of Automotive Semiconductor Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Time-multiplexed test access architecture for stacked integrated circuits.
IEICE Electron. Express, 2016

2015
Efficient diagnosis technique for aging defects on automotive semiconductor chips.
Proceedings of the 20th IEEE European Test Symposium, 2015

Scan-Puf: Puf Elements Selection Methods for Viable IC Identification.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory.
IEEE Trans. Computers, 2014

2012
Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress.
IEEE Trans. Instrum. Meas., 2012

2011
Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
On-Chip Support for NoC-Based SoC Debugging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A trial english class with a teaching assistant robot in elementary school.
Proceedings of the 5th ACM/IEEE International Conference on Human Robot Interaction, 2010

2009
An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008
Low-Cost Scan Test for IEEE-1500-Based SoC.
IEEE Trans. Instrum. Meas., 2008

Comparative study of effects of language instruction program using intelligence robot and multimedia on linguistic ability of young children.
Proceedings of the 17th IEEE International Symposium on Robot and Human Interactive Communication, 2008

An Efficient Secure Scan Design for an SoC Embedding AES Core.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC.
Proceedings of the 16th Asian Test Symposium, 2007

An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Hybrid test data compression technique for SOC scan testing.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

The educational use of home robots for children.
Proceedings of the IEEE International Workshop on Robot and Human Interactive Communication, 2005

2004
A new state assignment technique for testing and low power.
Proceedings of the 41th Design Automation Conference, 2004

2003
An Efficient Buffer Allocation Technique for Virtual Lanes in InfiniBand Networks.
Proceedings of the Web Communication Technologies and Internet-Related Social Issues, 2003

2002
A Genetic Algorithm for the Minimization of OPKFDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A New Boundary Matching Algorithm Based on Edge Detection.
Proceedings of the EurAsia-ICT 2002: Information and Communication Technology, 2002

A Simple Wrapped Core Linking Module for SoC Test Access.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Scalable data management using user-based caching and prefetching in distributed virtual environments.
Proceedings of the ACM Symposium on Virtual Reality Software and Technology, 2001

Minimization of OPKFDDs Using Genetic Algorithms.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

A Microcode-Based Memory BIST Implementing Modified March Algorithm.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A partial scan design by unifying structural analysis and testabilities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects.
Proceedings of the 2000 Design, 2000

1996
A New Complete Diagnosis Patterns for Wiring Interconnects.
Proceedings of the 33st Conference on Design Automation, 1996

1992
Parity bit calculation and test signal compaction for BIST applications.
J. Electron. Test., 1992

A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
Why is less information from logic simulation more useful in fault simulation?
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990


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