Hyunbean Yi

According to our database1, Hyunbean Yi authored at least 19 papers between 2003 and 2024.

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Bibliography

2024
Sow Posture Analysis and Estrus Prediction Using Closed-Circuit Television Cameras.
IEEE Access, 2024

2017
On Diagnosing the Aging Level of Automotive Semiconductor Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2015
Efficient diagnosis technique for aging defects on automotive semiconductor chips.
Proceedings of the 20th IEEE European Test Symposium, 2015

2012
A Failure Prediction Strategy for Transistor Aging.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
On-Chip Support for NoC-Based SoC Debugging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Aging test strategy and adaptive test scheduling for SoC failure prediction.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009
An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008
Low-Cost Scan Test for IEEE-1500-Based SoC.
IEEE Trans. Instrum. Meas., 2008

Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC.
Proceedings of the 16th Asian Test Symposium, 2007

An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Hybrid test data compression technique for SOC scan testing.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2003
An Efficient Buffer Allocation Technique for Virtual Lanes in InfiniBand Networks.
Proceedings of the Web Communication Technologies and Internet-Related Social Issues, 2003


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