Mukul Lokhande

Orcid: 0009-0001-8903-5159

According to our database1, Mukul Lokhande authored at least 23 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference.
CoRR, April, 2026

CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications.
CoRR, February, 2026

SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency.
CoRR, January, 2026

Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications.
CoRR, January, 2026

RAMAN: Resource-Efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-DesigN.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception Workloads.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025
FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration.
CoRR, November, 2025

Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads.
CoRR, October, 2025

ReLACE: A Resource-Efficient Low-Latency Cortical Acceleration Engine.
CoRR, October, 2025

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation.
CoRR, October, 2025

XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads.
CoRR, August, 2025

Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration.
CoRR, June, 2025

QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine.
CoRR, June, 2025

CORDIC Is All You Need.
CoRR, March, 2025

Retrospective: A CORDIC Based Configurable Activation Function for NN Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

HYDRA: A Resource-Efficient Hybrid Data-Multiplexed, Run-time Layer-Reconfigurable Compute Engine for DNN Acceleration.
Proceedings of the 2025 IEEE 19th International Conference on Industrial and Information Systems (ICIIS), 2025

A NOR8T SRAM Digital Compute-in-Memory Macro for Sparse and Scalable Edge-AI Processing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads.
CoRR, 2024

HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator.
CoRR, 2024

HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024


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