Munehiro Matsuura

J. Multiple Valued Log. Soft Comput., 2014

A Packet Classifier Based on Prefetching EVMDD (<i>k</i>) Machines.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K).

[BibT_eX]

[DOI]

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2013

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

A packet classifier using LUT cascades based on EVMDDS (k).

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An Architecture for IPv6 Lookup Using Parallel Index Generation Units.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2012

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

A Regular Expression Matching Circuit Based on a Decomposed Automaton.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

A Quaternary Decision Diagram Machine: Optimization of Its Code.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A regular expression matching using non-deterministic finite automaton.

[BibT_eX]

[DOI]

Hiroshi Nakahara

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

A Comparison of Architectures for Various Decision Diagram Machines.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

A Packet Classifier Using a Parallel Branching Program Machine.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

A Quaternary Decision Diagram Machine and the Optimization of its Code.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

A virus scanning engine using a parallel finite-input memory machine and MPUs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.

[BibT_eX]

[DOI]

Takaaki Nakamura

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

The Parallel Sieve Method for a Virus Scanning Engine.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A Parallel Branching Program Machine for Emulation of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2007

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2007

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Design Methods of Radix Converters Using Arithmetic Decompositions.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

A CAM Emulator Using Look-Up Table Cascades.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

An Implementation of an Address Generator Using Hash Memories.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

On Designs of Radix Converters Using Arithmetic Decompositions.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

A fast logic simulator using a look up table cascade emulator.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Average Path Length of Binary Decision Diagrams.

[BibT_eX]

[DOI]

Jon T. Butler

IEEE Trans. Computers, 2005

A Design Algorithm for Sequential Circuits Using LUT Rings.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A method to decompose multiple-output logic functions.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Evaluation of multiple-output logic functions using decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Bi-Partition of Shared Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Comparison of Decision Diagrams for Multiple-Output Logic Functions.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Representations of Logic Functions Using QRMDDs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

Realization of Multiple-Output Functions by Reconfigurable Cascades.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

Implementation of Multiple-Output Functions Using PQMDDs.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

A hardware simulation engine based on decision diagrams (short paper).

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Realization of Regular Ternary Logic Functions.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

On Decomposition of Kleene TDDs.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On properties of Kleene TDDs.

[BibT_eX]

[DOI]