Yoshifumi Kawamura

According to our database, Yoshifumi Kawamura authored at least 17 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

X-Band GaN Chipsets for Cost-Effective 20W T/R Modules.

Jun Kamioka, Yoshifumi Kawamura, Ryota Komaru, Masatake Hangai, Yoshitaka Kamo, Tetsuo Kodera, Shintaro Shinjo

IEICE Trans. Electron., 2022

2017

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.

Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.

Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Automatic rule registration and deletion function on a packet lookup engine LSI.

Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

2015

A broadband Rx band noise reduction circuit with CMOS switch for multi-band power amplifier.

Yoshifumi Kawamura, Shintaro Shinjo, Kazuhiro Iyomasa, Masakazu Hirobe, Katsuya Kato, Yoshinori Takahashi, Shigeo Yamabe, Kenichi Horiguchi, Morishige Hieda, Koji Yamanaka

Proceedings of the 2015 IEEE Radio and Wireless Symposium, 2015

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.

Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2014

The LSI implementation of a memory based field programmable device for MCU peripherals.

Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2012

HGPD: Human Gene and Protein Database, 2012 update.

Yukio Maruyama, Yoshifumi Kawamura, Tetsuo Nishikawa, Takao Isogai, Nobuo Nomura, Naoki Goshima

Nucleic Acids Res., 2012

2010

A Quaternary Decision Diagram Machine: Optimization of Its Code.

Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler

IEICE Trans. Inf. Syst., 2010

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

IEICE Trans. Inf. Syst., 2010

Basic Construction of Whole-Body Averaged SAR Estimation System Using Cylindrical-External Field Scanning for UHF Plane Wave Irradiation of Human Models.

Yoshifumi Kawamura, Takashi Hikage, Toshio Nojima

IEICE Trans. Commun., 2010

Experimental Quasi-Microwave Whole-Body Averaged SAR Estimation Method Using Cylindrical-External Field Scanning.

Yoshifumi Kawamura, Takashi Hikage, Toshio Nojima

IEICE Trans. Commun., 2010

2009

Human Gene and Protein Database (HGPD): a novel database presenting a large quantity of experiment-based results in human proteomics.

Yukio Maruyama, Ai Wakamatsu, Yoshifumi Kawamura, Kouichi Kimura, Jun-ichi Yamamoto, Tetsuo Nishikawa, Yasutomo Kisu, Sumio Sugano, Naoki Goshima, Takao Isogai, Nobuo Nomura

Nucleic Acids Res., 2009

A Quaternary Decision Diagram Machine and the Optimization of its Code.

Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler

Proceedings of the ISMVL 2009, 2009

A virus scanning engine using a parallel finite-input memory machine and MPUs.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

The Parallel Sieve Method for a Virus Scanning Engine.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A Parallel Branching Program Machine for Emulation of Sequential Circuits.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the Reconfigurable Computing: Architectures, 2009