Yukihiro Iguchi

According to our database, Yukihiro Iguchi authored at least 30 papers between 1989 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Classification Functions for Handwritten Digit Recognition.

Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi

IEICE Trans. Inf. Syst., 2021

A Design Method for Multiclass Classifiers.

Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

2020

Handwritten Digit Recognition Based on Classification Functions.

Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2017

An algorithm to find optimum support-reducing decompositions for index generation functions.

Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix.

Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions.

Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2011

A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus.

Koki Shirakawa, Takashi Uemura, Yukihiro Iguchi

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2008

On the Complexity of Error Detection Functions for Redundant Residue Number Systems.

Tsutomu Sasao, Yukihiro Iguchi

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

J. Multiple Valued Log. Soft Comput., 2007

Design Methods of Radix Converters Using Arithmetic Decompositions.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Inf. Syst., 2007

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA.

Hui Qin, Tsutomu Sasao, Yukihiro Iguchi

IEICE Trans. Inf. Syst., 2006

On Designs of Radix Converters Using Arithmetic Decompositions.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Hardware to Compute Walsh Coefficients.

Yukihiro Iguchi, Tsutomu Sasao

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

An FPGA design of AES encryption circuit with 128-bit keys.

Hui Qin, Tsutomu Sasao, Yukihiro Iguchi

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

On LUT Cascade Realizations of FIR Filters.

Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Fault Diagnosis for RAMs Using Walsh Spectrum.

Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao

IEICE Trans. Inf. Syst., 2004

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Evaluation of multiple-output logic functions using decision diagrams.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Bi-Partition of Shared Binary Decision Diagrams.

Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Comparison of Decision Diagrams for Multiple-Output Logic Functions.

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Representations of Logic Functions Using QRMDDs.

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

A Method for Storing Fail Bit Maps in Burn-in Memory Testers.

Atsumu Iseno, Yukihiro Iguchi

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Realization of Multiple-Output Functions by Reconfigurable Cascades.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

Implementation of Multiple-Output Functions Using PQMDDs.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

A hardware simulation engine based on decision diagrams (short paper).

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno

Proceedings of ASP-DAC 2000, 2000

1999

Realization of Regular Ternary Logic Functions.

Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

On Decomposition of Kleene TDDs.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On properties of Kleene TDDs.

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1989

Maximum PLA folding using inverters.

Yukihiro Iguchi, Masao Mukaidono

Syst. Comput. Jpn., 1989