Müstak E. Yalçin

Orcid: 0000-0003-3377-2560

Affiliations:
  • Istanbul Technical University, Department of Electronics and Communication Engineering


According to our database1, Müstak E. Yalçin authored at least 55 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FPGA-Based Implementation of a Matched Filter for Acoustic Shooter Localization System.
Proceedings of the 31st Signal Processing and Communications Applications Conference, 2023

An Open-Source eFPGA-based SoC Design for Computation Acceleration.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Optimization of the Eigenvalue Decomposition of Floating-Point Matrices on the TMS320C6672 Digital Signal Processor.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
The deep multichannel discrete-time cellular neural network model for classification.
Int. J. Circuit Theory Appl., 2022

2021
Delayed outputs fractional-order hyperchaotic systems synchronization for images encryption.
Multim. Tools Appl., 2021

2020
A new family of 5D, 6D, 7D and 8D hyperchaotic systems from the 4D hyperchaotic Vaidyanathan system, the dynamic analysis of the 8D hyperchaotic system with six positive Lyapunov exponents and an application to secure communication design.
Int. J. Model. Identif. Control., 2020

A new family of 9D and 10D hyperchaotic systems from the 8D hyperchaotic Benkouider system, the bifurcation analysis of the 10D hyperchaotic system, circuit design and an application to secure voice communication.
Int. J. Model. Identif. Control., 2020

A design of cellular automata-based PUF and its implementation on FPGA.
Int. J. Circuit Theory Appl., 2020

Chaos Synchronization of Fractional-Order Lur'e Systems.
Int. J. Bifurc. Chaos, 2020

GEZSAN - Real Time Spectrum Analyzer.
Proceedings of the 28th Signal Processing and Communications Applications Conference, 2020

A Hardware Accelerated Packet Classifier Design for A Network Router.
Proceedings of the 28th Signal Processing and Communications Applications Conference, 2020

2018
Design of an UWB-based indoor positioning system.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

Design of a pedestrian dead-reckoning system and comparison of methods on the system.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

A High Speed True Random Number Generator with Cellular Automata with Random Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Cellular Automata with Random Memory and Its Implementations.
Int. J. Bifurc. Chaos, 2017

Partially Reconfigurable IP Protection System with Ring Oscillator Based Physically Unclonable Functions.
Proceedings of the New Generation of CAS, 2017

Full digital implementation of a chaotic time-delay sampled-data system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A chaotic time-delay system based digital RNG and integrated autonomous test suite.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Emulating CNN with template learning on FPGA.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Realization of elementary cellular automata with random minimal memory.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Multi-scroll chaotic attractors from a generalized time-delay sampled-data system.
Int. J. Circuit Theory Appl., 2016

Asynchronous delay doubler and binary low-pass filter for a time-delay chaotic circuit.
Int. J. Circuit Theory Appl., 2016

2015
Attack on a Chaos-Based Random Number Generator Using Anticipating Synchronization.
Int. J. Bifurc. Chaos, 2015

Computer assisted sperm analysis system designed on a hybrid CPU + FPGA architecture.
Proceedings of the 2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Key generation and license authentication using physical unclonable functions.
Proceedings of the 2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Wave computer core using fixed-point arithmetic.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Cellular network of networks on dynamically partial reconfigurable FPGA.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
A Chaotic Time-Delay Sampled-Data System and Its Implementation.
Int. J. Bifurc. Chaos, 2014

Digital design of skeletonization.
Proceedings of the 2014 22nd Signal Processing and Communications Applications Conference (SIU), 2014

Realization of processing blocks of CNN based CASA system on CPU and FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
The Doppler Effect with input driven autowaves.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Throughput enhancement for a new time-delay sampled-data system based True Random Bit Generator.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Realization of preprocessing blocks of CNN based CASA system on FPGA.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A parallelized distance transformation architecture for FPGAs.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
An Application of Small-World Cellular Neural Networks on Odor Classification.
Int. J. Bifurc. Chaos, 2012

Hybrid processor population for odor processing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Implementation of a cellular neural network-based segmentation algorithm on the bio-inspired vision system.
J. Electronic Imaging, 2011

An active wave computing based path finding approach for 3-D environment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Randomly reconfigurable Cellular Neural Network.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Multiscroll Chaotic attractors from a Hysteresis Based Time-Delay Differential equation.
Int. J. Bifurc. Chaos, 2010

2009
An emulated digital wave computer core implementation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Synchronization of first-order time-delay systems generating n-scroll chaotic attractors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Increasing the Entropy of a Random Number Generator Using n-scroll Chaotic attractors.
Int. J. Bifurc. Chaos, 2007

2006
Spatiotemporal Pattern Formation on the ACE16K CNN Chip.
Int. J. Bifurc. Chaos, 2006

Multi-scroll and hypercube attractors from Josephson junctions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Spatiotemporal pattern formation in the ACE16k CNN chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
True random bit generation from a double-scroll attractor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Toward CNN chip-specific robustness.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Watermarking on CNN-UM for image and video authentication.
Int. J. Circuit Theory Appl., 2004

A double scroll based true random bit generator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Steady-State Analysis of Nonlinearly Coupled Chua's Circuits with Periodic Input.
Int. J. Bifurc. Chaos, 2003

Coupled chaotic simulated annealing processes.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Families of scroll Grid attractors.
Int. J. Bifurc. Chaos, 2002

2001
Master-Slave Synchronization of Lur'e Systems with Time-Delay.
Int. J. Bifurc. Chaos, 2001

1999
On the realization of n-scroll attractors.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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