N. Moorthy Muthukrishnan

According to our database1, N. Moorthy Muthukrishnan authored at least 13 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2018
Comparison of Voltage Charging Techniques to Increase the Life of Lead Acid Batteries.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

2012
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
A Prefix Based Reconfigurable Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
Proceedings of the International Symposium on Electronic System Design, 2011

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A low power, variable resolution two-step flash ADC.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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