Syed Ershad Ahmed

According to our database, Syed Ershad Ahmed authored at least 29 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications.

Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Avinash Bhat Pattaje, Suresh Nambi, Syed Ershad Ahmed

IEEE Embed. Syst. Lett., September, 2023

Design methodology for highly accurate approximate multipliers for error resilient applications.

Sahith Guturu, Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Syed Ershad Ahmed

Comput. Electr. Eng., September, 2023

A General Methodology to Optimize Flagged Constant Addition.

Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed

J. Circuits Syst. Comput., January, 2023

Improved approximate multiplier architecture for image processing and neural network applications.

Pramod Alamuri, Uppugunduru Anil Kumar, Vallepu Vannuru, Syed Ershad Ahmed

Microprocess. Microsystems, 2023

Power Efficient Approximate Ternary Subtractor for Image Processing Applications.

Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Design of Energy Efficient Posit Multiplier.

Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation.

Uppugunduru Anil Kumar, Sahith Guturu, Syed Ershad Ahmed

Microprocess. Microsystems, October, 2022

A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications.

Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed

J. Circuits Syst. Comput., 2022

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module.

Uppugunduru Anil Kumar, Sumit K. Chatterjee, Syed Ershad Ahmed

IEEE Embed. Syst. Lett., 2022

Compressor based hybrid approximate multiplier architectures with efficient error correction logic.

Anil Kumar Uppugunduru, S. Vignesh Bharadwaj, Syed Ershad Ahmed

Comput. Electr. Eng., 2022

2021

An Efficient Hardware Approach for Approximate Logarithmic Computation.

Syed Ershad Ahmed, Yerasuri Mohana Sri Krishna

J. Circuits Syst. Comput., 2021

DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications.

Suresh Nambi, Uppugunduru Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, Syed Ershad Ahmed

IEEE Embed. Syst. Lett., 2021

Lower part OR based Approximate Multiplier for Error Resilient Applications.

Uppugunduru Anil Kumar, Goli Naga Sandesh, Dhoti Ojusteja, Syed Ershad Ahmed

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Approximate Multiplier Architectures for Error Resilient Applications.

Uppugunduru Anil Kumar, Ratna Kumari Chintakunta, Sandeep Kumar, K. Jamal, Syed Ershad Ahmed

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Power-Efficient MLOA for error resilient applications.

Sahith Guturu, Anil Kumar Uppugunduru, Sridhar Thota, Syed Ershad Ahmed

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2019

An Improved Logarithmic Multiplier for Media Processing.

Syed Ershad Ahmed, M. B. Srinivas

J. Signal Process. Syst., 2019

2018

Improved designs of digit-by-digit decimal multiplier.

Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas

Integr., 2018

2016

A Hybrid Energy Efficient Digital Comparator.

Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An Iterative Logarithmic Multiplier with Improved Precision.

Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas

Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2014

A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter.

Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits.

Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2012

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.

Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.

Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.

Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the International Symposium on Electronic System Design, 2012

2011

A Prefix Based Reconfigurable Adder.

Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.

Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.

P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.

Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011