Naoki Fujieda

According to our database, Naoki Fujieda authored at least 24 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator.

Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe

IEICE Trans. Inf. Syst., December, 2023

A Novel Remote FPGA Lab Platform Using MCU-based Controller Board.

Naoki Fujieda, Atsuki Okuchi

Proceedings of the IEEE International Conference on Teaching, 2023

2022

An HLS implementation of on-the-fly randomness test for TRNGs.

Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa

Proceedings of the Tenth International Symposium on Computing and Networking, 2022

2021

An MMCM-based high-speed true random number generator for Xilinx FPGA.

Naoki Fujieda, Sogo Takashima

Int. J. Netw. Comput., 2021

A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC).

Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda

Int. J. Circuit Theory Appl., 2021

A Python-based evaluation framework for stochastic computing circuits on FPGA SoC.

Naoki Fujieda

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020

An Analysis of DCM-Based True Random Number Generator.

Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator.

Naoki Fujieda, Sogo Takashima

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs.

Naoki Fujieda

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

A light-weight implementation of latch-based true random number generator.

Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa

Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019

2018

Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.

Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2018

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.

Naoki Fujieda, Shuichi Ichikawa

IEICE Electron. Express, 2018

A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.

Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa

Proceedings of the TENCON 2018, 2018

An Analysis on Randomness of Path ORAM for Light-Weight Implementation.

Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017

A Virtual Cache for Overlapped Memory Accesses of Path ORAM.

Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa

Int. J. Netw. Comput., 2017

Evaluation of the hardwired sequence control system generated by high-level synthesis.

Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka

Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis.

Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

2016

Design and implementation of instruction indirection for embedded software obfuscation.

Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa

Microprocess. Microsystems, 2016

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM.

Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

A Complement to Enhanced Instruction Register File against Embedded Software Falsification.

Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa

Proceedings of the 5th Program Protection and Reverse Engineering Workshop, 2015

2013

An XOR-Based Approach to Merging Entries for Instruction Register Files.

Naoki Fujieda, Shuichi Ichikawa

Proceedings of the First International Symposium on Computing and Networking, 2013

2012

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.

Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism.

Mochamad Asri, Naoki Fujieda, Kenji Kise

Proceedings of the International SoC Design Conference, 2011

A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors.

Naoki Fujieda, Kenji Kise

Proceedings of the Second International Conference on Networking and Computing, 2011