Shuichi Ichikawa

According to our database1, Shuichi Ichikawa authored at least 39 papers between 1989 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
An Analysis of DCM-Based True Random Number Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Netlist-based Measures for Hardware Obfuscation: A Preliminary Study.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019
A light-weight implementation of latch-based true random number generator.
Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019

2018
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.
IEICE Trans. Inf. Syst., 2018

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.
IEICE Electron. Express, 2018

A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.
Proceedings of the TENCON 2018, 2018

An Analysis on Randomness of Path ORAM for Light-Weight Implementation.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
A Virtual Cache for Overlapped Memory Accesses of Path ORAM.
Int. J. Netw. Comput., 2017

Evaluation of the hardwired sequence control system generated by high-level synthesis.
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

2016
Design and implementation of instruction indirection for embedded software obfuscation.
Microprocess. Microsystems, 2016

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015
A Complement to Enhanced Instruction Register File against Embedded Software Falsification.
Proceedings of the 5th Program Protection and Reverse Engineering Workshop, 2015

2013
An XOR-Based Approach to Merging Entries for Instruction Register Files.
Proceedings of the First International Symposium on Computing and Networking, 2013

2012
FPGA Implementation of Metastability-Based True Random Number Generator.
IEICE Trans. Inf. Syst., 2012

Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning.
Proceedings of the Third International Conference on Networking and Computing, 2012

Reduction of Power Consumption in Key-specific AES Circuits.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
Foreword.
IEICE Trans. Inf. Syst., 2011

2009
Optimizing process allocation of parallel programs for heterogeneous clusters.
Concurr. Comput. Pract. Exp., 2009

Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study.
Proceedings of the 2009 International Conference on Complex, 2009

2008
Diversification of Processors Based on Redundancy in Instruction Set.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2006
Redundancy in Instruction Sequences of Computer Programs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm.
IEICE Trans. Inf. Syst., 2006

2005
Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation.
Parallel Comput., 2005

Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937.
IEICE Trans. Inf. Syst., 2005

2004
The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem.
IEICE Trans. Inf. Syst., 2004

The Evaluation of Davidson's Digital Signature Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004

An Execution-Time Estimation Model for Heterogeneous Clusters.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Data Dependent Circuit Design: A Case Study.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Redundancy in 3D Polygon Models and Its Application to Digital Signature.
Proceedings of the 10-th International Conference in Central Europe on Computer Graphics, 2002

Data Dependent Circuit for Subgraph Isomorphism Problem.
Proceedings of the Field-Programmable Logic and Applications, 2002

2000
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.
Proceedings of the Field-Programmable Logic and Applications, 2000

Hardware Accelerator for Subgraph Isomorphism Problems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1992
Evaluation of range-checking addressing modes and the architecture of FLATS2.
Systems and Computers in Japan, 1992

1991
Pseudorandom Rounding for Truncated Multipliers.
IEEE Trans. Computers, 1991

1990
Multiple instruction streams in a highly pipelined processor.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

1989
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines.
IEEE Trans. Computers, 1989

Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989


  Loading...