Shuichi Ichikawa

According to our database, Shuichi Ichikawa authored at least 43 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator.

Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe

IEICE Trans. Inf. Syst., December, 2023

Pseudo-Random Number Generation by Staggered Sampling of LFSR.

Shuichi Ichikawa

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2022

An HLS implementation of on-the-fly randomness test for TRNGs.

Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa

Proceedings of the Tenth International Symposium on Computing and Networking, 2022

2021

A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC).

Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda

Int. J. Circuit Theory Appl., 2021

2020

An Analysis of DCM-Based True Random Number Generator.

Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Netlist-based Measures for Hardware Obfuscation: A Preliminary Study.

Shotaro Yamada, Shuichi Ichikawa

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019

A light-weight implementation of latch-based true random number generator.

Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa

Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019

2018

Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.

Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2018

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.

Naoki Fujieda, Shuichi Ichikawa

IEICE Electron. Express, 2018

A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.

Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa

Proceedings of the TENCON 2018, 2018

An Analysis on Randomness of Path ORAM for Light-Weight Implementation.

Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017

A Virtual Cache for Overlapped Memory Accesses of Path ORAM.

Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa

Int. J. Netw. Comput., 2017

Evaluation of the hardwired sequence control system generated by high-level synthesis.

Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka

Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration.

Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis.

Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

2016

Design and implementation of instruction indirection for embedded software obfuscation.

Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa

Microprocess. Microsystems, 2016

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM.

Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

A Complement to Enhanced Instruction Register File against Embedded Software Falsification.

Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa

Proceedings of the 5th Program Protection and Reverse Engineering Workshop, 2015

2013

An XOR-Based Approach to Merging Entries for Instruction Register Files.

Naoki Fujieda, Shuichi Ichikawa

Proceedings of the First International Symposium on Computing and Networking, 2013

2012

FPGA Implementation of Metastability-Based True Random Number Generator.

Hisashi Hata, Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2012

Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning.

Satoru Tamura, Chikatoshi Yamada, Shuichi Ichikawa

Proceedings of the Third International Conference on Networking and Computing, 2012

Reduction of Power Consumption in Key-specific AES Circuits.

Shunsuke Matsuoka, Shuichi Ichikawa

Proceedings of the Third International Conference on Networking and Computing, 2012

2011

Foreword.

Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2011

2009

Optimizing process allocation of parallel programs for heterogeneous clusters.

Shuichi Ichikawa, Sho Takahashi, Yuu Kawai

Concurr. Comput. Pract. Exp., 2009

Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study.

Shuichi Ichikawa, Shoichiro Takagi

Proceedings of the 2009 International Conference on Complex, 2009

2008

Diversification of Processors Based on Redundancy in Instruction Set.

Shuichi Ichikawa, Takashi Sawada, Hisashi Hata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2006

Redundancy in Instruction Sequences of Computer Programs.

Kazuhiro Hattanda, Shuichi Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm.

Ryoichiro Atono, Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2006

2005

Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation.

Yoshinori Kishimoto, Shuichi Ichikawa

Parallel Comput., 2005

Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937.

Shiro Konuma, Shuichi Ichikawa

IEICE Trans. Inf. Syst., 2005

2004

The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem.

Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto

IEICE Trans. Inf. Syst., 2004

The Evaluation of Davidson's Digital Signature Scheme.

Kazuhiro Hattanda, Shuichi Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004

An Execution-Time Estimation Model for Heterogeneous Clusters.

Yoshinori Kishimoto, Shuichi Ichikawa

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Data Dependent Circuit Design: A Case Study.

Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

Redundancy in 3D Polygon Models and Its Application to Digital Signature.

Shuichi Ichikawa, H. Chiyama, K. Akabane

Proceedings of the 10-th International Conference in Central Europe on Computer Graphics, 2002

Data Dependent Circuit for Subgraph Isomorphism Problem.

Shuichi Ichikawa, Shoji Yamamoto

Proceedings of the Field-Programmable Logic and Applications, 2002

2000

Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.

Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi

Proceedings of the Field-Programmable Logic and Applications, 2000

Hardware Accelerator for Subgraph Isomorphism Problems.

Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1992

Evaluation of range-checking addressing modes and the architecture of FLATS2.

Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto

Syst. Comput. Jpn., 1992

1991

Pseudorandom Rounding for Truncated Multipliers.

Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa

IEEE Trans. Computers, 1991

1990

Multiple instruction streams in a highly pipelined processor.

Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto

Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

1989

CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines.

Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa

IEEE Trans. Computers, 1989

Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.

Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989