Naoshi Ishikawa
According to our database1,
Naoshi Ishikawa
authored at least 2 papers
between 2004 and 2013.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2013
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
2004
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits, 2004