Shunichi Iwata

According to our database, Shunichi Iwata authored at least 2 papers between 1989 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.

Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu

IEEE J. Solid State Circuits, 2004

1989

A 32-bit microprocessor with high performance bit-map manipulation instructions.

Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989