Kiyoshi Hayase

According to our database, Kiyoshi Hayase authored at least 4 papers between 1997 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2004

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.

Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu

IEEE J. Solid State Circuits, 2004

1997

Multiple-Valued Logic Minimization by Genetic Algorithms.

Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997