Nastaran Baradaran

According to our database1, Nastaran Baradaran authored at least 9 papers between 2003 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2008
A compiler approach to managing storage and memory bandwidth in configurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Exploiting parallelism in configurable architectures through custom array mapping.
IET Comput. Digit. Tech., 2007

2006
Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures.
Proceedings of the 2005 Design, 2005

2004
Extending the Applicability of Scalar Replacement to Multiple Induction Variables.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract.
Proceedings of the Field Programmable Logic and Application, 2004

2003
ECO: An Empirical-Based Compilation and Optimization System.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003


  Loading...