Pedro C. Diniz

According to our database1, Pedro C. Diniz authored at least 116 papers between 1995 and 2018.

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Bibliography

2018
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA.
Signal Processing Systems, 2018

RedThreads: An Interface for Application-Level Fault Detection/Correction Through Adaptive Redundant Multithreading.
International Journal of Parallel Programming, 2018

2016
Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach.
Softw., Pract. Exper., 2016

RedThreads: An Interface for Application-level Fault Detection/Correction through Adaptive Redundant Multithreading.
CoRR, 2016

Pragma-Controlled Source-to-Source Code Transformations for Robust Application Execution.
Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016

2015
Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware.
TRETS, 2015

Guest Editorial FPL 2013.
TRETS, 2015

Application-oriented cache memory configuration for energy efficiency in multi-cores.
IET Computers & Digital Techniques, 2015

Run-time Cache Configuration for the LEON-3 Embedded Processor.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Enabling application resilience through programming model based fault amelioration.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015

Atomic-delayed execution: A concurrent programming model for incomplete graph-based computations.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015

2014
A DSL for specifying run-time adaptations for embedded systems: an application to vehicle stereo navigation.
The Journal of Supercomputing, 2014

Addressing failures in exascale computing.
IJHPCA, 2014

Specifying Dynamic Adaptations for Embedded Applications Using a DSL.
Embedded Systems Letters, 2014

An evaluation of lazy fault detection based on Adaptive Redundant Multithreading.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Opportunistic application-level fault detection through adaptive redundant multithreading.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

On Expressing Strategies for Directive-Driven Multicore Programing Models.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

Evaluating High-Level Program Invariants Using Reconfigurable Hardware.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Controlling a complete hardware synthesis toolchain with LARA aspects.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Specifying Adaptations through a DSL with an Application to Mobile Robot Navigation.
Proceedings of the 2nd Symposium on Languages, Applications and Technologies, 2013

The MATISSE MATLAB compiler.
Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013

Robust graph traversal: Resiliency techniques for data intensive supercomputing.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

A Case for Adaptive Redundancy for HPC Resilience.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Poster: Programming Model Extensions for Resilience in Extreme Scale Computing.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Special session on "programming paradigms for reconfigurable multi-core embedded systems".
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Hardware/software specialization through aspects: The LARA approach.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Resiliency-aware Scheduling for reconfigurable VLIW processors.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Resiliency-aware scheduling: Resource allocation for hardened computation on configurable devices.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A resiliency-aware scheduling approach for FPGA configuration: Preliminary results.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Specifying Compiler Strategies for FPGA-based Systems.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Programming Model Extensions for Resilience in Extreme Scale Computing.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

A programming model for resilience in extreme scale computing.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2012

Controlling Hardware Synthesis with Aspects.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Experiments with the LARA aspect-oriented approach.
Proceedings of the Companion Volume of the 11th International Conference on Aspect-oriented Software Development, 2012

LARA: an aspect-oriented programming language for embedded systems.
Proceedings of the 11th International Conference on Aspect-oriented Software Development, 2012

2011
Domain-Specific Optimization of Signal Recognition Targeting FPGAs.
TRETS, 2011

Data Reorganization and Prefetching of Pointer-Based Data Structures.
IEEE Design & Test of Computers, 2011

Introduction.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

A Domain-Specific Language for the Specification of Adaptable Context Inference.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

2010
Preprocessing techniques for context recognition from accelerometer data.
Personal and Ubiquitous Computing, 2010

Providing user context for mobile and social networking applications.
Pervasive and Mobile Computing, 2010

Compiling for reconfigurable computing: A survey.
ACM Comput. Surv., 2010

High Performance Architectures and Compilers.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
Introduction to the Special Issue ARC'08.
TRETS, 2009

Guest Editorial.
Concurrency and Computation: Practice and Experience, 2009

Mobile Context Provider for Social Networking.
Proceedings of the On the Move to Meaningful Internet Systems: OTM 2009 Workshops, 2009

Context Inference for Mobile Applications in the UPCASE Project.
Proceedings of the Mobile Wireless Middleware, 2009

Code Transformations for Embedded Reconfigurable Computing Architectures.
Proceedings of the Generative and Transformational Techniques in Software Engineering III, 2009

Computation reuse in domain-specific optimization of signal recognition.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
A compiler approach to managing storage and memory bandwidth in configurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2008

The potential of computation reuse in high-level optimization of a signal recognition system.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Automatic Extraction of Process Control Flow from I/O Operations.
Proceedings of the Business Process Management, 6th International Conference, 2008

2007
Exploiting parallelism in configurable architectures through custom array mapping.
IET Computers & Digital Techniques, 2007

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures
CoRR, 2007

A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition.
Proceedings of the Computational Science, 2007

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
An overview of the ECO project.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system.
Microprocessors and Microsystems, 2005

Empirical Optimization for a Sparse Linear Solver: A Case Study.
International Journal of Parallel Programming, 2005

Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures.
Proceedings of the 2005 Design, 2005

2004
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.
IEEE Trans. Computers, 2004

Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques.
Proceedings of the Computer Systems: Architectures, 2004

Modeling Loop Unrolling: Approaches and Open Issues.
Proceedings of the Computer Systems: Architectures, 2004

Extending the Applicability of Scalar Replacement to Multiple Induction Variables.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

A Case Study Using Empirical Optimization for a Large, Engineering Application.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Eliminating synchronization bottlenecks using adaptive replication.
ACM Trans. Program. Lang. Syst., 2003

Increasing the Accuracy of Shape and Safety Analysis of Pointer-Based Codes.
Proceedings of the Languages and Compilers for Parallel Computing, 2003

ECO: An Empirical-Based Compilation and Optimization System.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Compiler Approach to Performance Prediction Using Empirical-Based Modeling.
Proceedings of the Computational Science - ICCS 2003, 2003

Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Compiler-generated communication for pipelined FPGA applications.
Proceedings of the 40th Design Automation Conference, 2003

Using estimates from behavioral synthesis tools in compiler-directed design space exploration.
Proceedings of the 40th Design Automation Conference, 2003

2002
A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.
Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Selector: A Language Construct for Developing Dynamic Applications.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

Data reorganization engines for the next generation of system-on-a-chip FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Coarse-Grain Pipelining on Multiple FPGA Architectures.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Bridging the Gap between Compilation and Synthesis in the DEFACTO System.
Proceedings of the Languages and Compilers for Parallel Computing, 2001

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Matching and searching analysis for parallel hardware implementation on FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

An External Memory Interface for FPGA-Based Computing Engines.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

A Behavioral Synthesis Estimation Interface for Configurable Computing.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Eliminating Synchronization Overhead in Automatically Parallelized Programs Using Dynamic Feedback.
ACM Trans. Comput. Syst., 1999

Synchronization transformations for parallel computing.
Concurrency - Practice and Experience, 1999

Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

DEFACTO: A Design Environment for Adaptive Computing Technology.
Proceedings of the Parallel and Distributed Processing, 1999

Eliminating synchronization bottlenecks in object-based programs using adaptive replication.
Proceedings of the 13th international conference on Supercomputing, 1999

1998
Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs.
J. Parallel Distrib. Comput., 1998

1997
Commutativity Analysis: A New Analysis Technique for Parallelizing Compilers.
ACM Trans. Program. Lang. Syst., 1997

On the Complexity of Commutativity Analysis.
Int. J. Found. Comput. Sci., 1997

Synchronization Transformations for Parallel Computing.
Proceedings of the Conference Record of POPL'97: The 24th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 1997

Dynamic Feedback: An Effective Technique for Adaptive Computing.
Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), 1997

1996
Commutativity Analysis: A New Analysis Framework for Parallelizing Compilers.
Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), 1996

Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Commutativity Analysis: A Technique for Automatically Parallelizing Pointer-Based Computations.
Proceedings of IPPS '96, 1996

Semantic Foundations of Commutativity Analysis.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

On the Complexity of Commutativity Analysis.
Proceedings of the Computing and Combinatorics, Second Annual International Conference, 1996

1995
Scheduling Iterative Task Computation on Message-Passing Architectures.
Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995

Efficient Parallelization of Relaxation Iterative Methods for Solving Banded Linear Systems on Multiprocessors.
Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995

Parallel Algorithms for Dynamically Partitioning Unstructured Grids.
Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995


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