Neelakantan Narasimman

According to our database, Neelakantan Narasimman authored at least 6 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS.

Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

2021

An Ultra-Low-Voltage VCO-Based ΔΣ Modulator Using Self-compensated Current Reference for Variation Tolerance.

Neelakantan Narasimman, Tony Tae-Hyoung Kim

Circuits Syst. Signal Process., 2021

A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications.

Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim

Proceedings of the 47th ESSCIRC 2021, 2021

2017

A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation.

Neelakantan Narasimman, Dipankar Nag, Kevin Tshun Chuan Chai, Tony T. Kim

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

An ultra-low voltage, VCO-based ADC with digital background calibration.

Neelakantan Narasimman, Tony T. Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation tolerance.

Neelakantan Narasimman, Tony T. Kim

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016