Tony Tae-Hyoung Kim
Orcid: 0000-0002-1779-1799
According to our database1,
Tony Tae-Hyoung Kim
authored at least 173 papers
between 2006 and 2024.
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Bibliography
2024
A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
A Dynamic Gesture Recognition Algorithm Using Single Halide Perovskite Photovoltaic Cell for Human-Machine Interaction.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN.
IEEE J. Solid State Circuits, February, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits, 2023
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 3.2-GHz 178-fs<sub>rms</sub> Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits, 2022
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 0.007 mm<sup>2</sup> 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Biomed. Circuits Syst., 2021
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.
Sensors, 2021
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst., 2021
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits, 2021
An Ultra-Low-Voltage VCO-Based ΔΣ Modulator Using Self-compensated Current Reference for Variation Tolerance.
Circuits Syst. Signal Process., 2021
9.7 A 184 µ W Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 137-μW 1.78-mm<sup>2</sup> 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Development of a Handheld Volumetric Photoacoustic Imaging System With a Central-Holed 2D Matrix Aperture.
IEEE Trans. Biomed. Eng., 2020
Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems.
Sensors, 2020
A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations.
IEEE Access, 2020
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
Design and Characterization of Radiation-Hardened MCU for Space Application using Error Correction SRAM and Glitch Removal Clock Buffer Cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation.
Microelectron. J., 2019
Microelectron. J., 2019
An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI.
IEEE J. Solid State Circuits, 2019
Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Continuous wave laser excitation based portable optoacoustic imaging system for melanoma detection.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
2018
An Area and Energy Efficient Ultra-Low Voltage Level Shifter With Pass Transistor and Reduced-Swing Output Buffer in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An Area Efficient 1024-Point Low Power Radix-2<sup>2</sup> FFT Processor With Feed-Forward Multiple Delay Commutators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 88% Efficiency 0.1-300-µW Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes.
IEEE J. Solid State Circuits, 2018
A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS.
IEEE J. Solid State Circuits, 2018
Proceedings of the International SoC Design Conference, 2018
Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects.
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 %C-300 %C).
IEEE Trans. Very Large Scale Integr. Syst., 2017
Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers in 3DICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Self-Adaptive Time-Based MPPT With 96.2% Tracking Efficiency and a Wide Tracking Range of 10 µA to 1 mA for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Microelectron. J., 2017
Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE J. Solid State Circuits, 2016
Circuits Syst. Signal Process., 2016
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm<sup>2</sup> per channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A time-based self-adaptive energy-harvesting MPPT with 5.1-µW power consumption and a wide tracking range of 10-µA to 1-mA.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation tolerance.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
An isolated PoR based pulse generator for TEG energy harvesting with minimum startup of 150 mV and maximum series resistance of 600 Ω.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm<sup>2</sup> per Channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
A 0.6-V power efficient digital LDO with 99.7% current efficiency utilizing load current aware clock modulation for fast transient response.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
SRAM devices and circuits optimization toward energy efficiency in multi-V<sub>th</sub> CMOS.
Microelectron. J., 2015
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
An output feedback-based start-up technique with automatic disabling for battery-less energy harvesters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression.
Proceedings of the ESSCIRC Conference 2015, 2015
A 76% efficiency boost converter with 220mV self-startup and 2nW quiescent power for high resistance thermo-electric energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Micro, 2014
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring.
IEEE J. Solid State Circuits, 2014
Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C.
IEEE J. Solid State Circuits, 2014
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance.
IEEE J. Solid State Circuits, 2014
An area- and power-efficient FIFO with error-reduced data compression for image/video processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Design of SRAM PUF with improved uniformity and reliability utilizing device aging effect.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.
IEEE J. Solid State Circuits, 2013
A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset.
Proceedings of the European Solid-State Device Research Conference, 2013
Design of a power-efficient CAM using automated background checking scheme for small match line swing.
Proceedings of the ESSCIRC 2013, 2013
2012
An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of V<sub>MIN</sub> Degradation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells.
Proceedings of the International SoC Design Conference, 2012
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Microelectron. Reliab., 2010
A 9T subthreshold SRAM bitcell with data-independent bitline leakage for improved bitline swing and variation tolerance.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V<sub>min</sub> Lowering Techniques and Deep Sleep Mode.
IEEE J. Solid State Circuits, 2009
An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits.
IEEE J. Solid State Circuits, 2008
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
Proceedings of the 43rd Design Automation Conference, 2006