Nick Huang

According to our database1, Nick Huang authored at least 7 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.
IEEE J. Solid State Circuits, 2014

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits, 2012

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009
Extracting interconnect capacitance sensitivity to linewidth variation.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009


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