Hyo-Gyuem Rhew
According to our database1,
Hyo-Gyuem Rhew
authored at least 14 papers
between 2010 and 2024.
Collaborative distances:
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Bibliography
2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2016
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2014
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management.
IEEE J. Solid State Circuits, 2014
2012
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders.
Proceedings of the Symposium on VLSI Circuits, 2012
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2010
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC.
IEEE J. Solid State Circuits, 2010