Ullas Singh

According to our database1, Ullas Singh authored at least 21 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2016
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

2015
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.
IEEE J. Solid State Circuits, 2014

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.
IEEE J. Solid State Circuits, 2013

An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition.
IEEE J. Solid State Circuits, 2013

A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits, 2012

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.
IEEE J. Solid State Circuits, 2011

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.
IEEE J. Solid State Circuits, 2010

2009
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS.
IEEE J. Solid State Circuits, 2006

2005
High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz.
IEEE J. Solid State Circuits, 2005

2003
Design of CMOS CML circuits for high-speed broadband communications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Dynamics of high-frequency CMOS dividers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
New structures for very high-frequency CMOS clock dividers.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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