Bo Zhang
Orcid: 0009-0003-1215-3389Affiliations:
- Broadcom Corporation, Irvine, CA, USA
- Rockwell Semiconductor Inc., Newport Beach, CA, USA (1996 - 2000)
- Oregon State University, Corvallis, OR, USA (PhD 1996)
According to our database1,
Bo Zhang
authored at least 21 papers
between 2007 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2024
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology.
IEEE J. Solid State Circuits, January, 2024
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2017
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.
IEEE J. Solid State Circuits, 2015
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2013
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits, 2012
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.
IEEE J. Solid State Circuits, 2010
2009
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS.
IEEE J. Solid State Circuits, 2007