Shantanu Dutt

According to our database, Shantanu Dutt authored at least 70 papers between 1988 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Limiting Interconnect Heating in Power-Driven Physical Synthesis.

Xiuyan Zhang, Shantanu Dutt

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

2021

On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis.

Shantanu Dutt, Xiuyan Zhang, Ouwen Shi

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2019

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding.

Xiuyan Zhang, Ouwen Shi, Jian Xu, Shantanu Dutt

J. Low Power Electron., 2019

2018

A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis.

Shantanu Dutt, Ouwen Shi

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Power-delay product based resource library construction for effective power optimization in HLS.

Shantanu Dutt, Ouwen Shi

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis.

Ouwen Shi, Shantanu Dutt

J. Low Power Electron., 2016

2015

Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs.

Enzo Tartaglione, Shantanu Dutt

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

New Algorithmic Techniques for Complex EDA Problems.

Shantanu Dutt, Dinesh P. Mehta, Gi-Joon Nam

VLSI Design, 2014

2013

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm.

Huan Ren, Shantanu Dutt

VLSI Design, 2013

2011

A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement.

Huan Ren, Shantanu Dutt

IEEE Trans. Very Large Scale Integr. Syst., 2011

Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction.

Shantanu Dutt, Huan Ren

IEEE Trans. Very Large Scale Integr. Syst., 2011

Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous V_dd, V_th Assignments, Gate Sizing, and Placement.

Huan Ren, Shantanu Dutt

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Timing yield optimization via discrete gate sizing using globally-informed delay PDFs.

Shantanu Dutt, Huan Ren

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.

Shantanu Dutt, Li Li

ACM Trans. Reconfigurable Technol. Syst., 2009

Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach.

Shantanu Dutt, Yang Dai, Huan Ren, Joel Fontanarosa

Proceedings of the Bioinformatics and Computational Biology, 2009

2008

Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.

Shantanu Dutt, Vinay Verma, Vishal Suthar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure.

Huan Ren, Shantanu Dutt

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

An efficient delay-optimal distributed termination detection algorithm.

Nihar R. Mahapatra, Shantanu Dutt

J. Parallel Distributed Comput., 2007

Constraint satisfaction in incremental placement with application to performance optimization under power constraints.

Huan Ren, Shantanu Dutt

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.

Vishal Suthar, Shantanu Dutt

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A network-flow approach to timing-driven incremental placement for ASICs.

Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream.

Federico Rota, Shantanu Dutt, Sahithi Krishna

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.

Vishal Suthar, Shantanu Dutt

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations.

Shantanu Dutt, Hasan Arslan

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.

Vishal Suthar, Shantanu Dutt

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems.

Nihar R. Mahapatra, Shantanu Dutt

Parallel Comput., 2004

A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits.

Hasan Arslan, Shantanu Dutt

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance.

Hasan Arslan, Shantanu Dutt

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Roving testing using new built-in-self-tester designs for FPGAs.

Vinay Verma, Shantanu Dutt

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Efficient on-line testing of FPGAs with provable diagnosabilities.

Vinay Verma, Shantanu Dutt, Vishal Suthar

Proceedings of the 41th Design Automation Conference, 2004

2003

ROAD : An Order-Impervious Optimal Detailed Router for FPGAs.

Hasan Arslan, Shantanu Dutt

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002

A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.

Shantanu Dutt, Vinay Verma, Hasan Arslan

ACM Trans. Design Autom. Electr. Syst., 2002

Cluster-aware iterative improvement techniques for partitioning large VLSI circuits.

Shantanu Dutt, Wenyong Deng

ACM Trans. Design Autom. Electr. Syst., 2002

Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control.

Ke Zhong, Shantanu Dutt

Proceedings of the 39th Design Automation Conference, 2002

2001

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays.

Nihar R. Mahapatra, Shantanu Dutt

J. Parallel Distributed Comput., 2001

A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs.

Vinay Verma, Shantanu Dutt

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Probability-based approaches to VLSI circuit partitioning.

Shantanu Dutt, Wenyong Deng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing.

Nihar R. Mahapatra, Shantanu Dutt

Int. J. Found. Comput. Sci., 2000

Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views.

Ke Zhong, Shantanu Dutt

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Partitioning using second-order information and stochastic-gainfunctions.

Shantanu Dutt, Hasan Arslan, Halim Theny

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays.

Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Digest of Papers: FTCS-29, 1999

1998

Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.

Fran Hanchek, Shantanu Dutt

IEEE Trans. Computers, 1998

Partitioning using second-order information and stochastic-gain functions.

Shantanu Dutt, Halim Theny

Proceedings of the 1998 International Symposium on Physical Design, 1998

1997

REMOD: a new methodology for designing fault-tolerant arithmetic circuits.

Shantanu Dutt, Fran Hanchek

IEEE Trans. Very Large Scale Integr. Syst., 1997

Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search.

Nihar R. Mahapatra, Shantanu Dutt

IEEE Trans. Parallel Distributed Syst., 1997

Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance.

Shantanu Dutt, Nihar R. Mahapatra

IEEE Trans. Computers, 1997

Partitioning around roadblocks: tackling constraints with intermediate relaxations.

Shantanu Dutt, Halim Theny

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations.

Shantanu Dutt, Fikri T. Assaad

IEEE Trans. Computers, 1996

Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.

Fran Hanchek, Shantanu Dutt

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Are There Advantages to High-Dimension Architectures? Analysis of <i>k</i>-ary <i>n</i>-Cubes for the Class of Parallel Divide-and-Conquer Algorithms.

Shantanu Dutt, Nam Trinh

Proceedings of the 10th international conference on Supercomputing, 1996

Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.

Fran Hancheck, Shantanu Dutt

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

VLSI circuit partitioning by cluster-removal using iterative improvement techniques.

Shantanu Dutt, Wenyong Deng

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Digest of Papers: FTCS-26, 1996

A Probability-Based Approach to VLSI Circuit Partitioning.

Shantanu Dutt, Wenyong Deng

Proceedings of the 33st Conference on Design Automation, 1996

1994

Scalable Load Balancing Strategies for Parallel A* Algorithms.

Shantanu Dutt, Nihar R. Mahapatra

J. Parallel Distributed Comput., 1994

New Anticipatory Load Balancing Strategies for Parallel A* Algorithms.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Workshop on Parallel Processing of Discrete Optimization Problems, 1994

1993

Scalable Duplicate Pruning Strategies for Parallel A* Graph Search.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors.

Shantanu Dutt

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Parallel A^* Algorithms and Their Performance on Hypercube Multiprocessors.

Shantanu Dutt, Nihar R. Mahapatra

Proceedings of the Seventh International Parallel Processing Symposium, 1993

New faster Kernighan-Lin-type graph-partitioning algorithms.

Shantanu Dutt

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Some Practical Issues in the Design of Fault-Tolerant Multiprocessors.

Shantanu Dutt, John P. Hayes

IEEE Trans. Computers, 1992

More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication.

Fikri T. Assaad, Shantanu Dutt

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Subcube Allocation in Hypercube Computers.

Shantanu Dutt, John P. Hayes

IEEE Trans. Computers, 1991

Designing Fault-Tolerant System Using Automorphisms.

Shantanu Dutt, John P. Hayes

J. Parallel Distributed Comput., 1991

1990

Designing and reconfiguring fault-tolerant multiprocessor systems.

Shantanu Dutt

PhD thesis, 1990

On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures.

Shantanu Dutt, John P. Hayes

IEEE Trans. Computers, 1990

1989

An automorphic approach to the design of fault-tolerant multiprocessors.

Shantanu Dutt, John P. Hayes

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures.

Shantanu Dutt, John P. Hayes

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

On allocating subcubes in a hypercube multiprocessor.

Shantanu Dutt, John P. Hayes

Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988