Niichi Itoh

According to our database1, Niichi Itoh authored at least 2 papers between 2001 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2001
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree.
IEEE J. Solid State Circuits, 2001


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