Koji Nii
Orcid: 0000-0002-9986-5308
According to our database1,
Koji Nii
authored at least 90 papers
between 1990 and 2024.
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Bibliography
2024
A 3-nm FinFET 27.6-Mbit/mm<sup>2</sup> Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.
IEEE J. Solid State Circuits, April, 2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.
IEEE J. Solid State Circuits, 2023
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
2020
A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash<sup>®</sup>-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron., 2019
2018
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.
IEEE Trans. Multi Scale Comput. Syst., 2018
Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators.
IET Circuits Devices Syst., 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.
IEICE Trans. Electron., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A 6.05-Mb/mm<sup>2</sup> 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 5.92-Mb/mm<sup>2</sup> 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
1.8 Mbit/mm<sup>2</sup> ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2015
An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the ESSCIRC Conference 2015, 2015
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
Proceedings of the Symposium on VLSI Circuits, 2014
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
The LSI implementation of a memory based field programmable device for MCU peripherals.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
IEEE J. Solid State Circuits, 2013
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Electron., 2012
A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
Proceedings of the IEEE 25th International SOC Conference, 2012
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.
IEEE J. Solid State Circuits, 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology.
IEICE Trans. Electron., 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
Area Optimization in 6T and 8T SRAM Cells Considering <i>V</i><sub>th</sub> Variation in Future Processes.
IEICE Trans. Electron., 2007
Area Comparison between 6T and 8T SRAM Cells in Dual-<i>V</i><sub>dd</sub> Scheme and DVS Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.
IEEE J. Solid State Circuits, 2006
A 0.3-V Operating, <i>V</i><sub>th</sub>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
IEEE J. Solid State Circuits, 2004
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1995
IEEE J. Solid State Circuits, March, 1995
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1990
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990