Yasumasa Tsukamoto
According to our database1,
Yasumasa Tsukamoto
authored at least 35 papers
between 1995 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
2020
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 5.92-Mb/mm<sup>2</sup> 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
1.8 Mbit/mm<sup>2</sup> ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
Proceedings of the Symposium on VLSI Circuits, 2014
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
IEEE J. Solid State Circuits, 2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
Proceedings of the IEEE 25th International SOC Conference, 2012
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits, 2009
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
IEEE J. Solid State Circuits, 2004
1995
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995