Nikil D. Dutt
Orcid: 0000-0002-3060-8119Affiliations:
- University of California, Irvine, Department of Computer Science, CA, USA
According to our database1,
Nikil D. Dutt
authored at least 558 papers
between 1989 and 2024.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2014, "For contributions to embedded architecture exploration, and service to electronic design automation and embedded systems.".
IEEE Fellow
IEEE Fellow 2008, "For contributions to architecture description languages for the design and exploration of customized processors".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on ics.uci.edu
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on orcid.org
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on id.loc.gov
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on d-nb.info
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on cecs.uci.edu
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on dl.acm.org
On csauthors.net:
Bibliography
2024
Integrating Wearable Sensor Data and Self-reported Diaries for Personalized Affect Forecasting.
CoRR, 2024
Context-Aware Stress Monitoring using Wearable and Mobile Technologies in Everyday Settings.
CoRR, 2024
2023
IEEE Embed. Syst. Lett., December, 2023
DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference.
IEEE Embed. Syst. Lett., December, 2023
A Deep Learning-based PPG Quality Assessment Approach for Heart Rate and Heart Rate Variability.
ACM Trans. Comput. Heal., October, 2023
Frontiers Digit. Health, May, 2023
IEEE Trans. Emerg. Top. Comput., 2023
EASYR: Energy-Efficient Adaptive System Reconfiguration for Dynamic Deadlines in Autonomous Driving on Multicore Processors.
ACM Trans. Embed. Comput. Syst., 2023
IACR Cryptol. ePrint Arch., 2023
Reducing Intraspecies and Interspecies Covariate Shift in Traumatic Brain Injury EEG of Humans and Mice Using Transfer Euclidean Alignment.
CoRR, 2023
Robust Detection of Social Isolation in Older Adults by Combining Biometrics with Social Interaction Data.
Proceedings of the 2023 IEEE International Conference on Smart Computing, 2023
Error Resilience Evaluation of Approximate Storage in the Motion Compensation of VVC Decoders.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the 15th ACM/USENIX Workshop on Hot Topics in Storage and File Systems, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Tutorial: MARS: A Framework for Runtime Monitoring, Modeling, and Management of Realtime Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
Active Reinforcement Learning for Personalized Stress Monitoring in Everyday Settings.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2023
Loneliness Forecasting Using Multi-modal Wearable and Mobile Sensing in Everyday Settings.
Proceedings of the 19th IEEE International Conference on Body Sensor Networks, 2023
Impact of COVID-19 Pandemic on Sleep Including HRV and Physical Activity as Mediators: A Causal ML Approach.
Proceedings of the 19th IEEE International Conference on Body Sensor Networks, 2023
2022
Online Learning for Orchestration of Inference in Multi-user End-edge-cloud Networks.
ACM Trans. Embed. Comput. Syst., November, 2022
IEEE Trans. Parallel Distributed Syst., 2022
The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing.
IEEE Trans. Emerg. Top. Comput., 2022
Personal mental health navigator: Harnessing the power of data, personal models, and health cybernetics to promote psychological well-being.
Frontiers Digit. Health, 2022
Efficient Personalized Learning for Wearable Health Applications using HyperDimensional Computing.
CoRR, 2022
Objective Prediction of Tomorrow's Affect Using Multi-Modal Physiological Data and Personal Chronicles: A Study of Monitoring College Student Well-being in 2020.
CoRR, 2022
Proceedings of the 23rd IEEE International Symposium on a World of Wireless, 2022
Proceedings of the IEEE Real-Time Systems Symposium, 2022
ProSwap: Period-aware Proactive Swapping to Maximize Embedded Application Performance.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022
Hybrid Learning for Orchestrating Deep Learning Inference in Multi-user Edge-cloud Networks.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
CARLsim 6: An Open Source Library for Large-Scale, Biologically Detailed Spiking Neural Network Simulation.
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Composing Graphical Models with Generative Adversarial Networks for EEG Signal Modeling.
Proceedings of the IEEE International Conference on Acoustics, 2022
Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Label Alignment Improves EEG-based Machine Learning-based Classification of Traumatic Brain Injury.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
Novel Blood Pressure Waveform Reconstruction from Photoplethysmography using Cycle Generative Adversarial Networks.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
AMSER: Adaptive Multimodal Sensing for Energy Efficient and Resilient eHealth Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
J. Signal Process. Syst., 2021
ACM Trans. Embed. Comput. Syst., 2021
Chauffeur: Benchmark Suite for Design and End-to-End Analysis of Self-Driving Vehicles on Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2021
ACM Trans. Embed. Comput. Syst., 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
IEEE Embed. Syst. Lett., 2021
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition.
IEEE Embed. Syst. Lett., 2021
AMSER: Adaptive Multi-modal Sensing for Energy Efficient and Resilient eHealth Systems.
CoRR, 2021
P2E-WGAN: ECG waveform synthesis from PPG with conditional wasserstein generative adversarial networks.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021
Energy-Efficient Adaptive System Reconfiguration for Dynamic Deadlines in Autonomous Driving.
Proceedings of the 24th IEEE International Symposium on Real-Time Distributed Computing, 2021
NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
Data Collection and Labeling of Real-Time IoT-Enabled Bio-Signals in Everyday Settings for Mental Health Improvement.
Proceedings of the GoodIT '21: Conference on Information Technology for Social Good, 2021
Investigation of Machine Learning and Deep Learning Approaches for Detection of Mild Traumatic Brain Injury from Human Sleep Electroencephalogram.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Detection of COVID-19 Using Heart Rate and Blood Pressure: Lessons Learned from Patients with ARDS.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Proceedings of the A Journey of Embedded and Cyber-Physical Systems, 2021
pyEDA: An Open-Source Python Toolkit for Pre-processing and Feature Extraction of Electrodermal Activity.
Proceedings of the 12th International Conference on Ambient Systems, 2021
Towards Smart and Efficient Health Monitoring Using Edge-enabled Situational-awareness.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Edge-Assisted Control for Healthcare Internet of Things: A Case Study on PPG-Based Early Warning Score.
ACM Trans. Internet Things, 2020
Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography.
ACM Trans. Embed. Comput. Syst., 2020
ACM Trans. Cyber Phys. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
An Efficient and Robust Deep Learning Method with 1-D Octave Convolution to Extract Fetal Electrocardiogram.
Sensors, 2020
Investigation of Machine Learning Approaches for Traumatic Brain Injury Classification via EEG Assessment in Mice.
Sensors, 2020
IACR Cryptol. ePrint Arch., 2020
ACM Trans. Comput. Heal., 2020
IEEE Embed. Syst. Lett., 2020
Personal Mental Health Navigator: Harnessing the Power of Data, Personal Models, and Health Cybernetics to Promote Psychological Well-being.
CoRR, 2020
CoRR, 2020
The Causality Inference of Public Interest in Restaurants and Bars on COVID-19 Daily Cases in the US: A Google Trends Analysis.
CoRR, 2020
GSR Analysis for Stress: Development and Validation of an Open Source Tool for Noisy Naturalistic GSR Data.
CoRR, 2020
Continuous Non-Invasive Blood Pressure Monitoring: A Methodological Review on Measurement Techniques.
IEEE Access, 2020
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020
R-TOD: Real-Time Object Detector with Minimized End-to-End Delay for Autonomous Driving.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
PyCARL: A PyNN Interface for Hardware-Software Co-Simulation of Spiking Neural Network.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 11th International Green and Sustainable Computing Workshops, 2020
Classification of Electroencephalogram in a Mouse Model of Traumatic Brain Injury Using Machine Learning Approaches<sup>*</sup>.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Dynamic iFogSim: A Framework for Full-Stack Simulation of Dynamic Resource Management in IoT Systems.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020
Proceedings of the Extended Abstracts of the 2020 CHI Conference on Human Factors in Computing Systems, 2020
2019
HESSLE-FREE: <u>He</u>terogeneou<u>s</u> <u>S</u>ystems <u>Le</u>veraging <u>F</u>uzzy Control for <u>R</u>untim<u>e</u> Resourc<u>e</u> Management.
ACM Trans. Embed. Comput. Syst., 2019
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router.
IEEE Trans. Computers, 2019
PLoS Comput. Biol., 2019
J. Syst. Archit., 2019
The power impact of hardware and software actuators on self-adaptable many-core systems.
J. Syst. Archit., 2019
Effect of Soft Errors in Iterative Learning Control and Compensation using Cross-layer Approach.
Int. J. Comput. Commun. Control, 2019
Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors.
IACR Cryptol. ePrint Arch., 2019
ACM Comput. Surv., 2019
CoRR, 2019
CoRR, 2019
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing.
IEEE Comput. Archit. Lett., 2019
Personalized Maternal Sleep Quality Assessment: An Objective IoT-based Longitudinal Study.
IEEE Access, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Global Communications Conference, 2019
Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the 4th IEEE/ACM International Conference on Connected Health: Applications, 2019
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019
Energy-efficient and Reliable Wearable Internet-of-Things through Fog-Assisted Dynamic Goal Management.
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019
2018
Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores.
IEEE Trans. Multi Scale Comput. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018
Proc. IEEE, 2018
Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout.
Neural Networks, 2018
Microprocess. Microsystems, 2018
IACR Cryptol. ePrint Arch., 2018
IEEE Embed. Syst. Lett., 2018
Des. Autom. Embed. Syst., 2018
Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
A Recurrent Neural Network Based Model of Predictive Smooth Pursuit Eye Movement in Primates.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the IEEE Global Communications Conference, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Approximation-aware coordinated power/performance management for heterogeneous multi-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Embed. Syst. Lett., 2017
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning.
CoRR, 2017
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Dependability evaluation of SISO control-theoretic power managers for processor architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017
QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
ML-Gov: a machine learning enhanced integrated CPU-GPU DVFS governor for mobile gaming.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Trends, challenges and needs for lattice-based cryptography implementations: special session.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Proceedings of the 2017 International Conference on Compilers, 2017
2016
SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores.
ACM Trans. Embed. Comput. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
Int. J. Comput. Commun. Control, 2016
IET Comput. Digit. Tech., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016
HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile Gaming.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016
Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation.
ACM Trans. Embed. Comput. Syst., 2015
ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings.
IEEE Trans. Computers, 2015
ACM Trans. Archit. Code Optim., 2015
A GPU-accelerated cortical neural network model for visually guided robot navigation.
Neural Networks, 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
it Inf. Technol., 2015
IEEE Embed. Syst. Lett., 2015
IEEE Embed. Syst. Lett., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 Information Theory and Applications Workshop, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Orchestrated application quality and energy storage management in solar-powered embedded systems.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Models, abstractions, and architectures: the missing links in cyber-physical systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2014
<i>SPMCloud</i>: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud.
ACM Trans. Design Autom. Electr. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Efficient Spiking Neural Network Model of Pattern Motion Selectivity in Visual Cortex.
Neuroinformatics, 2014
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Quality-aware mobile graphics workload characterization for energy-efficient DVFS design.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule.
Neural Networks, 2013
A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior.
Frontiers Comput. Neurosci., 2013
Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution.
Des. Autom. Embed. Syst., 2013
Proceedings of the 2013 IEEE 6th International Conference on Service-Oriented Computing and Applications, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.
Proceedings of the International Green Computing Conference, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
EAVE: Error-Aware Video Encoding Supporting Extended Energy/QoS Trade-offs for Mobile Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Internet Serv. Appl., 2012
IEEE Embed. Syst. Lett., 2012
IEEE Embed. Syst. Lett., 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Proceedings of the 11th Workshop on Adaptive and Reflective Middleware, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
<i>HaVOC</i>: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Frontiers Neuroinformatics, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the HOST 2011, 2011
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the Formal Modeling: Actors, Open Systems, Biological Systems, 2011
2010
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2010
Partitioning techniques for partially protected caches in resource-constrained embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2010
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the HOST 2010, 2010
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 2010 International Conference on Compilers, 2010
PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2009
System-level PVT variation-aware power exploration of on-chip communication architectures.
ACM Trans. Design Autom. Electr. Syst., 2009
Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.
IEEE Trans. Ind. Informatics, 2009
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2009
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors.
Neural Networks, 2009
Int. J. Parallel Program., 2009
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata.
Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009
A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors.
Proceedings of the International Joint Conference on Neural Networks, 2009
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Specification-driven directed test generation for validation of pipelined processors.
ACM Trans. Design Autom. Electr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.
ACM Trans. Embed. Comput. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Real-time analysis of resource-constrained distributed systems by simulation-guided model checking.
SIGBED Rev., 2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
Int. J. Parallel Program., 2008
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
Int. J. Embed. Syst., 2008
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach.
Proceedings of the 16th International Conference on Multimedia 2008, 2008
Compiler driven data layout optimization for regular/irregular array access patterns.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.
Proceedings of the Distributed Embedded Systems: Design, 2008
Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems.
Proceedings of the Distributed Embedded Systems: Design, 2008
Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices.
IEEE J. Sel. Areas Commun., 2007
Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.
Des. Autom. Embed. Syst., 2007
Adv. Multim., 2007
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements.
Proceedings of the Parallel Computing: Architectures, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
System level power estimation methodology with H.264 decoder prediction IP case study.
Proceedings of the 25th International Conference on Computer Design, 2007
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2007
A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems.
Proceedings of the Formal Methods for Open Object-Based Distributed Systems, 2007
Performance estimation of distributed real-time embedded systems by discrete event simulations.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
Proceedings of the 44th Design Automation Conference, 2007
Software controlled memory layout reorganization for irregular array access patterns.
Proceedings of the 2007 International Conference on Compilers, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Compiler Aided Design of Embedded Computers.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006
ACM Trans. Embed. Comput. Syst., 2006
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the Embedded Computer Systems: Architectures, 2006
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006
Proceedings of the 5th International Symposium on Parallel and Distributed Computing (ISPDC 2006), 2006
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Automatic identification of application-specific functional units with architecturally visible storage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
Proceedings of the 43rd Design Automation Conference, 2006
System-level power-performance trade-offs in bus matrix communication architecture synthesis.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 3rd IEEE Consumer Communications and Networking Conference, 2006
Mitigating soft error failures for multimedia applications by selective data protection.
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.
IEEE Trans. Computers, 2005
Int. J. Embed. Syst., 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices.
Proceedings of the Networking, 2005
An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.
Proceedings of the 2005 Design, 2005
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Compilation techniques for energy reduction in horizontally partitioned cache architectures.
Proceedings of the 2005 International Conference on Compilers, 2005
Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Functional verification of programmable embedded architectures - a top-down approach.
Springer, ISBN: 978-0-387-26143-0, 2005
2004
ACM Trans. Design Autom. Electr. Syst., 2004
ACM Trans. Embed. Comput. Syst., 2004
ACM Trans. Embed. Comput. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Using global code motions to improve the quality of results for high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEICE Trans. Inf. Syst., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Extending the transaction level modeling approach for fast communication architecture exploration.
Proceedings of the 41th Design Automation Conference, 2004
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2003
ACM Trans. Embed. Comput. Syst., 2003
IEEE Des. Test Comput., 2003
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications.
Des. Autom. Embed. Syst., 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Proceedings of the Eleventh ACM International Conference on Multimedia, 2003
Proceedings of the 2003 Conference on Languages, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Data Organization Exploration for Low-Energy Address Buses.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Proceedings of the 2003 Design, 2003
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs.
Proceedings of the 2003 Design, 2003
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.
Proceedings of the International Conference on Compilers, 2003
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
Memory architecture exploration for programmable embedded systems.
Kluwer, ISBN: 978-1-4020-7324-3, 2003
2002
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002
Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Automatic functional test program generation for pipelined processors using model checking.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the High Performance Computing, 2002
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.
Proceedings of the 2002 Design, 2002
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
Proceedings of the 39th Design Automation Conference, 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
J. Syst. Archit., 2001
IEEE Des. Test Comput., 2001
Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors.
IEEE Des. Test Comput., 2001
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Functional abstraction driven design space exploration of heterogeneous programmable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Conditional speculation and its effects on performance and area for high-level snthesis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98).
IEEE Trans. Very Large Scale Integr. Syst., 2000
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.
ACM Trans. Design Autom. Electr. Syst., 2000
ACM Trans. Design Autom. Electr. Syst., 2000
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000
Customizing Software Toolkits for Embedded Systems-On-Chip.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000
System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Proceedings of the 2000 Design, 2000
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Program path analysis to bound cache-related preemption delay in preemptive real-time systems.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Computers, 1999
On the rapid prototyping and design of a wireless communication system on a chip (abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability.
Proceedings of the 1999 Design, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the Languages and Compilers for Parallel Computing, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
1997
Memory data organization for improved cache performance in embedded processor applications.
ACM Trans. Design Autom. Electr. Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Symposium on System Synthesis, 1997
Proceedings of the Solving Irregularly Structured Problems in Parallel, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the European Design and Test Conference, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
ACM Trans. Design Autom. Electr. Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of IPPS '96, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
A hypergraph-based model for port allocation on multiple-register-file VLIW architectures.
Int. J. Parallel Program., 1995
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
An algorithm for the allocation of functional units from realistic RT component libraries.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Integrating program transformations in the memory-based synthesis of image and video algorithms.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
A Unified code generation approach using mutation scheduling.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the European Design Automation Conference 1993, 1993
High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
A Representation for the Binding of RT-Component Functionality to HDL Behavior.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
1992
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992
Benchmarking and the Art of Syntesis Tool Comparison.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the conference on European design automation, 1992
1991
Proceedings of the 28th Design Automation Conference, 1991
1990
Proceedings of the 1990 Internation Conference on Computer Languages, 1990
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990
1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989